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Ion beam milling is successfully implemented for smoothing roughness of the fin sidewalls for the FinFETs with poly-crystalline TiN metal gate (MG). The Vt variability is improved significantly by smoothing the fin roughness without degradation of the carrier mobility. The suppressed Vt variability is interpreted as improved uniformity in the grain orientation of TiN which causes work function variation...
FinFETs with an amorphous metal gate (MG) are fabricated on silicon-on-thin-buried-oxide (SOTB) wafers for realizing both low variability and tunable threshold voltage (Vt) necessary for multiple Vt solution. The FinFETs with an amorphous TaSiN MG record the lowest on-state drain current (Ion) variability (0.37 %µm) in comparison to bulk and SOI planar MOSFETs thanks to the suppressed variability...
For the first time, we have successfully fabricated the Vth controllable connected multigate FinFET on the world's thinnest 9-nm-thick extremely thin (ET) BOX SOI substrate. It was experimentally demonstrated that, by controlling the back (substrate) bias, the Vth of the FinFET on the ETBOX is flexibly tuned from low Vth to high Vth with keeping low sub-threshold slope.
One of the biggest challenges for the VLSI circuits with 20-nm-technology nodes and beyond is to overcome the issue of a catastrophic increase in power dissipation of the circuit due to short channel effects (SCEs). Fortunately, double-gate FinFETs have a promising potential to overcome this issue due to their superior SCE immunity even with an undoped channel thanks to the 3D structure. This paper...
Influence of NiSi S/D incorporation on parasitic resistance (Rpara) fluctuation of FinFETs was investigated in detail. While the NiSi S/D enhances the on current of the FinFET thanks to the Rpara reduction, it also causes additional Rpara fluctuation. Through analysis of correlation of Rpara with fin thickness and gate-to-NiSi offset fluctuation, it is revealed that NiSi/n+-Si contact resistance component...
PVD-TiN gate FinFET SRAM half-cells with different β-ratios and fin-height controlled transistors have successfully been fabricated using orientation-dependent wet etching and selective recess RIE. It was found that read static noise margin (SNM) increases significantly by controlling β from 1 to 2. With further increasing β, read SNM increases slightly. On the other hand, write margin shows weak...
The Vt variability in scaled FinFETs with gate length (Lg) down to 25 nm was systematically investigated, for the first time. By investigating the gate oxide thickness (Tox) dependence of Vt variation (VTV), the gate-stack origin, i.e., work-function variation (WFV) and gate oxide charge (Qox) variation (OCV) origin VTV were successfully separated. It was found that the atomically flat Si-fin sidewall...
The paper have demonstrated the effect of the resistivity reduction of the atomic layer deposited (ALD) TiN film using TDMAT precursor by modifying the NH3 process (both initial exposure and post deposition annealing (PDA) processes). It was found that the resistivity of the ALD TiN was significantly reduced by extending NH3 exposure time and increasing PDA temperature by 700°C. Moreover, by employing...
Variability of the TiN FinFET SRAM cell performance is comprehensively studied. It is found that the static noise margin (SNM) variation of the SRAM cell is due to the Vth variation of FinFETs caused by the work function variation (WFV) of the TiN metal-gate. It is experimentally demonstrated that the Vth-controllable independent-double-gate (IDG) FinFET technology successfully compensates not only...
IN this paper, various FinFETs with the different fin-width and gate-length were fabricated and characterised using SEM and cross-sectional STEM imaging. It was found that the standard deviations of the Vth of the pMOS and nMOS FinFETs are almost the same and the main Vth variation source was the work function variation of the TiN metal gate. Also, the on-current variation for TiN FinFETs was predominated...
The nanoscale TiN wet etching and its application for FinFET fabrication have been systematically investigated. It is experimentally found that the TiN side-etching can be controlled to be half of TiN thickness with precise time control. By using the developed nanoscale TiN wet etching technique, sub-30-nm physical gate length FinFETs, 100-nm tall fin CMOS inverters and SRAM half-cells have successfully...
FinFET performance variability is comprehensively investigated for undoped/doped channels with various gate materials. By evaluating the influence of channel doping, fluctuation of gate length and that of fin thickness, it is found that gate workfunction variation (WFV) is the dominant source of Vt variation for the undoped FinFET and that the WFV increases with scaling of gate area. In addition,...
SRAM cells with Vth-controllable independent double-gate (IDG) FinFETs have been successfully fabricated. The performance of the fabricated SRAM cell with various circuit topologies has been investigated comprehensively. Both a reduction of leakage current and an enhancement of read and write noise margins have been successfully demonstrated by introducing the IDG FinFETs into the SRAM cells.
This work introduces an analytical approach to model the random threshold voltage (Vth) fluctuations in emerging high-k/metal-gate devices caused by the dependency of metal work-function (WF) on its grain orientations. It is shown that such variations can be modeled by a multi-nomial distribution where the key parameters of its probability distribution function (pdf) can be calculated in terms of...
The parasitic resistance of the FinFET is investigated by the measurement based analysis. The RS/D model suggests that careful optimization as to the NiSi incorporation is necessary for the effective Rp reduction. The Rext seriously increases the Rp for TfinLt25 nm and also causes the Rp variability due to the Tfin variation.
The logic gate threshold voltage controllable single metal gate FinFET CMOS inverter constructed by the 3T-PMOS and 4T-NMOS have successfully been fabricated. The accurate current matching and the logic gate threshold voltage tuning by Vg2 in the 4T-NMOS have been demonstrated. A higher WF metal would be more suitable for the proposed FinFET CMOS.
We propose a flexible-pass-gate (Flex-PG) FinFET SRAM to enhance both the read and write noise margins. The flip-flop in the Flex-PG SRAM cell consists of usual FinFETs while its pass gates consist of Vth-controllable four-terminal (4T) FinFETs with independent double-gates. We experimentally demonstrate that the proposed Flex-PG SRAM increases both the read and write margins by controlling the Vth...
TiN gate FinFET SRAM half-cells with different ??-ratios from 1-3 have successfully been fabricated by using the orientation dependent wet etching and conventional reactive sputtering, for the first time. It is experimentally found that static noise margin (SNM)at read condition increases with increasing ??-ratio due to the strength of pull-down transistor. To overcome SRAM cell size increment with...
An independent-gate four-terminal FinFET SRAM have been successfully fabricated for drastic leakage current reduction. The new SRAM is consisted of a four-terminal (4T-) FinFET which has a flexible Vth controllability. The 4T-FinFET with a TiN metal gate is fabricated by a newly developed gate separation etching process. By appropriately controlling the Vth of the 4T-FinFET, we have successfully demonstrated...
As one of promising metal gate materials, PVD TiN has widely been studied for conventional bulk-planar CMOS devices due to its high purity [1, 2]. However, there have been no systematical studies regarding the PVD TiN gate work function (tin) control using the nitrogen gas flow ratio (Rfrac12 = N2/(Ar+N2)) in the sputtering. In this paper, we present the Rfrac12 controlled tunable work function PVD...
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