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A simulation methodology for FinFET stress and crystallographic orientation engineering is introduced and applied to tall scaled p- and n-type FinFETs with strained nitride layers on (001) wafers. The methodology consists of combining 3D mechanical stress simulation with 2D Monte Carlo device simulation where an averaged channel stress tensor is used. 50 nm down to 10 nm gate-length p- and n-type...
This paper presents an innovative 3D CMOS 6T SRAM cell design in multi-channel (MC) FET technology by well adapting the number of channels per device. A simulation model for the 45 nm MCFET has been developed based on silicon measurements. The electrical results validated by simulations, exhibit more than 25% power dissipation reduction and 17% cell stability improvement for the same area and read...
We have presented the high performance pMOSFET with embedded SiGe (eSiGe) technique which is applicable to 32 nm node ground rule (dense gate space). In general, close eSiGe S/D structure to the channel improves pMOSFET performance because of higher strain in the channel. However, we found the relation between boron diffusion modulation in SiGe region and short channel effect (SCE) in the context...
This paper reports on the fabrication, experimental characterization and data transmission application of a double-gate movable body FET. As its name suggests, the proposed movable-body Micro-Electro-Mechanical FET (MB-MEMFET) is a hybrid MEMS-semiconductor device that, in contrast with previously reported Suspended-Gate MOSFET, has a movable body separated by nano-size air gaps from two lateral fixed...
A silicon swimming robot or pond skating device has been demonstrated. It floats on liquid surfaces using surface tension and is capable of movement using electrowetting on dielectric (EWOD) based propulsion. Its dimensions are 6 times 9 mm with a thickness of 380 mum. The driving mechanism involves the trapping of air bubbles within the liquid onto the hydrophobic surface of the device with the subsequent...
The influence of gate underlap on the electrical properties is analyzed. Both simulation results and experimental data show that in a device with gate underlap, accumulation-mode (AM) devices have a higher current drive, lower source and drain resistance and less process variability than inversion-mode (IM) FETs.
We integrate carbon nanotube (CNT) fabrication with commercial CMOS VLSI fabrication on a single substrate suitable for emerging hybrid nanotechnology applications. This co-integration combines the inherent advantages of CMOS and CNTs. These emerging applications include CNT optical, biological, chemical, and gas sensors that require complex CMOS electronics for sensor control, calibration, and signal...
A strong reduction of MOSFET low-frequency noise under switched gate bias conditions is observed for forward substrate bias. The effect of forward substrate bias is significantly larger in switched compared to constant gate bias conditions. Experimental results reveal that forward substrate bias is most effective when applied during the off-state of the transistor. This finding is explained by the...
More than a decade of research in the field of thermal, motion, and vibrational energy scavenging has yielded increasing power output and smaller embodiments. Power management circuits for rectification and DC-DC conversion are becoming able to efficiently convert the power from these energy scavengers. This paper summarizes recent energy scavenging results and their power management circuits.
In order to continue the scaling of silicon-based CMOS and maintain the historic progress in information processing and transmission, innovative device structures and new materials have to be created. A channel material with high mobility and therefore high injection velocity can increase on current and reduce delay. Currently, strained-Si is the dominant technology for high performance MOSFETs and...
In recent years, printing has received substantial interest as a technique for realizing low cost, large area electronic systems. Printing allows the use of purely additive processing, thus lowering process complexity and material usage. Coupled with the use of low-cost substrates such as plastic, metal foils, etc., it is expected that printed electronics will enable the realization of a wide range...
The quantitative evaluation of the impact of key sources of statistical variability (SV) are presented for LP nMOSFETs corresponding to 45 nm, 32 nm and 22 nm technology generation transistors with bulk, thin body (TB) SOI and double gate (DG) device architectures respectively. The simulation results indicate that TBSOI and DG are not only resistant to random dopant induced variability, but also are...
We fabricated a novel type MOSFET with inversion layer source/drain extensions formed by Cs implantation and segregation at SiO2/Si interfaces beside the gate and demonstrate that it has significant immunity to short channel effect, gate induced drain leakage, and transient enhanced diffusion of channel boron impurities, compared to conventional MOSFETs. The stability of Cs in the device is also confirmed...
This work proposes a Bulk+ planar fully depleted ldquofoldedrdquo technology as an innovative cost worthy solution for upcoming low power nodes. We report a detailed fabrication method, combining advanced selective epitaxy faceting and SON (Silicon-On-Nothing) process, to provide thin film/thin BOX devices with improved transistor gain beta for a given designed footprint Wdesign. We compare the fabrication...
Ultralow off-current (Ioff les 1 pA/mum) ldquosilicon on thin BOX (SOTB)rdquo CMOSFETs were fabricated in 65-nm technology. Gate-induced drain leakage (GIDL) was adequately reduced by controlling the gate-overlap length with an additional offset spacer. Small threshold-voltage (Vth) variation under a wide-range back-gate-bias (Vbg) condition and suppressed Ioff variation by Vbg control were demonstrated...
In this paper, a deterministic approach to electron transport based on the spherical harmonics expansion of the Boltzmann equation is presented for SiGe heterojunction bipolar transistors. In order to take into account the position-dependent minima of the valleys of the conduction band, a new formulation of the discretized scattering integral for non-aligned and non-equidistant energy grids is developed...
In this paper, we investigate the dependence between the performance of multiple-gate FETs (dasiaMuGFETspsila) and the thickness of their plasma-enhanced-ALD (PE-ALD) TiN gate electrode. We show that very thin PE-ALD-TiN gate electrodes allow improved short channel effect (SCE) control and enhanced performance in n-channel MuGFETs without mobility modification. Based on the electrical characterization...
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