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We have developed strained-Si-on-nothing (SSON) MOSFETs with a gate all around (GAA) structure by using selective wet etching and doped poly-Si CVD techniques. The nano-beam diffraction (NBD) method was employed to directly evaluate the strain within the SSON channels. We have demonstrated the enhanced drive current, Id, of the GAA SSON MOSFETs over that of relaxed control MOSFETs.
A new method to extract RF parameters of planar channel MOSFETs through RF device modeling was proposed, and also the model was verified up to 20 GHz. It was thought the proposed method and models can be applied consistently to extract resistances.
This paper propose a model for nonadiabatic electron capture and present a simulation that can explain the experimental results. It was found that the capture accuracy can be higher than the thermal-equilibrium limit. These findings might open up a way of utilizing a non-equilibrium process to break the thermal-equilibrium limit in the ultimate charge control.
Various sizes of erbium silicided n-/p-type Schottky barrier MOSFETs are manufactured from 20 um to 7 nm. The manufactured SB-MOSFETs show excellent DIBL and subthreshold swing characteristics due to the existence of Schottky barrier between source and channel. It is found that the control of the Schottky barrier height between silicon and ErSi1.7 is the key factor for the increase of drive current...
Metal-oxide-silicon(MOS) capacitors incorporating 2 ~ 3 germanium (Ge) quantum dots (QDs) in the gate oxide were fabricated to exhibit multi-peak negative differential resistance (NDR) for multiple-value memories and logics. The tunneling current through the Ge-QD MOS capacitors is theoretically and experimentally studied. We found that negative differential resistance (NDR) arises from the interdot...
A new 2-bit/cell SONOS flash memory device is designed and simulated with a numerical simulation tool. The device has a recessed channel and a supplementary gate named a select gate. The select gate is appended to enhance the program efficiency by source-side injection (SSI) as well as to separate the charge storage nodes physically. The designed structure looks like a folded form of conventional...
Graphene, a recently discovered form of carbon, revealed many unique properties, including extremely high electron mobility of ~15000 cm2/Vs at room temperature (RT). We have experimentally studied the thermal conductivity of graphene suspended over a trench in silicon (Si) wafer. It was found for a given set of samples that RT thermal conductivity of graphene is in the range ~ 3080 - 5150 W/mK. The...
A novel hetero-tunnel transistor (HtFET) with a heterostructure parallel to the dielectric interface is proposed for low-voltage (low-power) electronics. Its potential of scaling Vdd down to 0.2 V is examined with quantum mechanical tunneling theory. Data from high-K metal-gate, Si on Ge hetero-tunnel transistor verifies the HtFET concept.
Enhanced non-volatile memory device characteristics of crystallite Al2O3 film (??900??C) with a large hysteresis memory window of ??V ?? 9.8 V under a gate voltage of ??15 V have been observed due to crystallization of the Al2O3 film. The hysteresis memory window of ??V ?? 3.8 V under a gate voltage of ??10 V is also observed. Both program and erase speeds of ??V~2.6V@1s are achieved under Fowler-Nordheim...
In this paper, a novel vertical channel double-gate 1T-DRAM cell transistor with nonvolatile charge storage node was proposed. Excellent sensing margin and good retention characteristic have been achieved by programming charge in the storage node. Relatively long channel double-gate 1T-DRAM cell with fully depleted thin body on bulk Si wafer without increasing cell size could be achieved. It was found...
In this paper the authors proposed a new method to estimate ??Vth from floating gate NAND flash memory, using charge pumping method to a cell string. Although any cells in a string are selected, this method could be roughly applied to extract ??Vth. After P/E cycling, the charge pumping method also estimated ??Vth with moderate pulse amplitude (in this work, at 4.5 V or 5 V). By using our proposed...
We have proposed cone SONOS memory structure previously. The point of the structure is field concentration effect in two directions. Among the two, concentration of source to drain direction is critical in program operation. Simulation result shows the shape of narrow drain leads to great memory performance. Fabricated structure shows the same results. In this report, simplified program simulation...
Double quantum dots (DQDs) have been studied as attractive candidates for charge qubits. Initially, GaAs-based DQDs formed by means of surface gates depletion were studied because many parameters are tunable after their fabrications [1]. However, silicon-based DQDs are more promising for charge qubits because of the absence ofpiezoelectric electron-phonon coupling, and the effect of phonon localization...
Engineering materials at the nanoscale by combining controlled nanomaterial synthesis and directed assembly methods offers the potential to create new electronic and optical devices with improved performance and functionality. Semiconductor nanowires have been of particular interest as a model system for studying new physical phenomena arising from their scaled geometries as well as for applications...
Atomistic 3D device simulations of 20nm-gate-length planar vs. tri-gate bulk MOSFETs with identical nominal retrograde-well and source/drain doping profiles show that the tri-gate structure is more robust to random dopant fluctuation (RDF) effects, i.e. threshold voltage (VTH) lowering and variation. VTH lowering is verified to be due primarily to channel/well RDF. For the tri-gate bulk MOSFET, VTH...
A major problem of usual current measurement setup is the severe limitations on the bandwidth due to room temperature electronics. This restricts the practical measurement rate to below 10 Hz and makes impossible to observe the evolution of a quantum state in real time. Here we describe a measurement on a silicon single electron transistor (SET) carried out using a custom CMOS measurement circuit...
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