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The silicon IC technology continues to scale following Moore's law for over fifty years. Now, we are approaching a critical crossroad as we are about at the limit of conventional optical lithography the enabler of our business. Besides lithography, new materials, device structures, and interconnect schemes must also be developed in order to keep us on the scaling curve. In addition, we not only have...
This invited paper gives an overview of road safety statistics and a summary of advanced driver assistance systems that have recently been deployed. The science and technology behind popular automotive vision systems, such as traffic sign recognition, is briefly explained and the processing requirements of vision algorithms are presented in the context of automotive environment. There are many opportunities...
We report the demonstration of a new contact resistance reduction technology for Si:C S/D using Tellurium (Te) implant and segregation. When integrated in a novel process flow featuring a single-metal platinum-based silicide (PtSi) contact technology, independent control of SBH in n- and p-FinFETs can be achieved. A low electron SBH of 120 meV is attained for n-FinFETs with Si:C S/D using PtSi and...
A novel high temperature silicide process using millisecond anneal is reported. Superior thermal stability, film properties (Rs, surface roughness) and low contact resistivity to n+ silicon of <; 1 Ωμm2 is demonstrated with milli-second silicide anneal which results in grain size change and potential strain incorporation resulting in overall enhanced performance.
Future generation graphics applications require more than 1TB/s memory bandwidth with a constant power budget as in today's systems. In contrast, future mobile applications require power optimized memory interfaces that can provide sufficient memory bandwidth on the order of 25GB/s. The difference in the optimization criteria results in different design challenges and consequently, different architectural...
Improved resistive switching memory characteristics in a W/Ti/Ta2O5/W device with a small size of 150 nm have been investigated for the first time. TEM image shows amorphous Ta2O5 film with a thickness of ~7 nm. Memory device has a good repeatable bipolar memory behavior and a large sensing margin of ~2000. The memory device has shown good endurance of at least 104 cycles and excellent data retention...
In terms of defect generation and redistribution, the electrical forming process and filamentary conduction lead conventional RRAM cells to low yield, high operation current, and large operation variations [1-3]. Recently, emerging RRAM cells based on the redox reaction mechanism were proposed to eliminate electrical forming process [4]. However, the endurance was below few thousands cycles and device...
Low power and reliable “Fab-friendly” resistance switching memory devices (ReRAM) are achieved by controlling composition and morphology of simple binary transition-metal oxides (MeOx) and metal-nitride electrodes (Ti-N) through physical vapor deposition (PVD) methods. Adjusting PVD deposition parameters influence crystalline structure, surface morphology, and stoichiometry, which subsequently influence...
The effects of ultrathin EOT on the carrier mobility in bulk-Si, UTBOX-FDSOI and SiGe-QW pFET devices were compared. The mobility is found to decrease dramatically with the EOT (Tinv) as a result of stronger charge and surface roughness scattering at thinner SiOx interface layers irrespective of the device technology. UTBOX-FDSOI and bulk-Si nFETs have identical mobility values (190 cm2/Vs) at Tinv...
Electron transport in graphene has attracted intense research interest due to its exotic quantum transport behavior discovered in this system in the relation to the device applications beyond CMOS operation. In this presentation, we will discuss ballistic charge transport and quantum carrier collimation in graphene, both of which appear even at room temperature. In addition, we will discuss electronic...
In this paper, we present a new erase gate disturb mechanism during programming of selected cell for split-gate Flash memory. This type of disturb occurs on the programmed cell sharing the same erase gate as the selected cell. The disturb is due to electron-loss from floating gate to erase gate caused by low-field Fowler-Norheim (F-N) tunneling. We proposed a method that adds extra bias voltages at...
In this work we investigate the correlation between hydrogen content and leakage current through the Al2O3 layers of TANOS memories. We put in evidence that retention of TANOS memories is improved with the decrease of H concentration in the Al2O3 layer. Using atomistic simulations consolidated by detailed Al2O3 physico-chemical analyses, we find that interstitial H produces a midgap trap likely to...
This work establishes an accurate 3D physical model with quantum approach to analyze the small size nanocrystal (NC) nonvolatile memory. The basic memory performance, programming and erasing, is studied in detail. The trapping efficiency, Coulomb blockade and quantum confinement are the main factors affecting the memory performance. Tradeoff between these factors exists on the selection of NC size...
This work demonstrates a new type of SONOS memory in which there are no junctions. These junction-less (JL) devices are realized on vertical Si nanowire gate all-around structure with channel dimension down to 20nm and have comparable electrical characteristics (SS <; 70mV/dec, leakage current <;1×10-12 A and a memory window of 3.2V with 1ms P/E) with the junction based wire SONOS. Being free...
This paper gives a summary on SOI based Smart Power technologies. The benefit of SOI is explained by reviewing the basic power device concepts. SOI enables full dielectric isolation of devices. In power applications this can be used to build products with improved EMC, improved robustness. Another dominant aspect is that devices can be biased above the supply voltage or below the ground voltage, without...
A new interface defect spectroscopy method based on variable height charge pumping capable of observing the amphoteric nature of Si/SiO2 interface states in production quality sub-micron devices is demonstrated. It can help to resolve the long standing debate about the true nature of interface states.
The expectation for SiC devices in advanced power electronics applications for saving energy has been still larger. The 4H-SiC planer MOSFETs with high blocking voltage (1300V) and large current (40A) were fabricated. In addition, we have succeeded in fabricating the larger current (300A) 4H-SiC trench MOSFET with low-on resistance (2.6mΩcm2). And, regarding high-temperature operation, SiC IPMs can...
For decades, Moore's law transistor cost scaling created a vibrant ecosystem of foundries, fabless design houses, IDMs, and suppliers. Each of these parties shared in the abundant economic benefits of the transistor cost scaling enabled by Moore's law. This led to specialization within each layer and vertical segment of the supply chain wherein rigid technical interfaces allowed uni-dimensional technology...
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