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We fabricated Fully-Depleted (FD) nMOSFETs on strain-SOI substrates (sSOI), exceeding regular FDSOI devices by +20% in nMOS ON-state current (ION) and +18% in SRAM read current. For pMOSFETs on sSOI, the integration of Si0.57Ge0.43 by the Ge-enrichment technique (in so-called sSGOI) is the solution to reach the performance of Si0.78Ge0.22 channels built on SOI (SGOI) in terms of short channel hole...
This paper summarizes the technological developments carried out in STMicroelectronics to raise the fT / fMAX of SiGe HBTs up to ~ 300 GHz / 400 GHz. The noise and power performance in the W-band of different SiGe HBT generations are compared along with CML ring oscillators and circuit results up to the D band.
This work presents design methodology of on-wafer calibration standards covering frequencies up to 110 GHz and optimized for the BiCMOS processes. We discuss such topics as layout optimization of distributed and lumped standards, measurement and verification of electrical characteristics along with the definition of the on-wafer calibration reference impedance and measurement reference plane. Also,...
Calibrated 3-D numerical simulations supported by DC experimental data are employed to quantify the impact of the key layout and technology parameters on the thermal resistance of state-of-the-art SiGe heterojunction bipolar transistors (HBTs) so as to define proper optimization criteria. The geometry parameters of a simple scalable model are optimized to describe the thermal resistance dependence...
On-wafer RF calibration methods are compared to the conventional Impedance Standard Substrate (ISS) calibration combined with a dummies de-embedding approach for transistors of an advanced BiCMOS process. We discuss the design of customized calibration standards addressing specifics of the silicon BiCMOS process. Our results show that on-wafer calibration methods are the most suitable approaches for...
A 160-GHz downconversion front-end for imaging arrays fabricated in a SiGe HBT technology is presented. The front-end features a fully differential architecture compatible with balanced on or off-chip antennas consisting of a three-stage LNA with 24 dB gain and Gilbert-cell mixer operating from -7dBm fundamental LO signal. The downconverter consumes 50 mA from a 3.3V supply and requires is 0.1 mm2...
This paper presents a status of the HICUM model development activities (within the DOTFIVE project) for future technologies. Physics based scalable model libraries are realized for two of the most advanced SiGe:C HBT processes currently available. The parameter extraction methodology is described via two meaningful examples. Measurement and simulation comparisons are shown.
This paper summarizes the work carried out to improve performances of a conventional double-polysilicon FSA-SEG SiGe:C HBT towards 400 GHz fMAX. The technological optimization strategy is discussed and electrical characteristics are presented. A record peak fMAX of 423 GHz (fT = 273 GHz) is demonstrated in SiGe:C HBT technology.
Reliability performances of fully self aligned heterojunction bipolar transistors were investigated under high current and voltage stress conditions. We point out in this paper that generation-recombination traps induced by reverse bias stress can be repaired by forward bias. This is possible thanks to high enough device temperature (strong self-heating condition). Low frequency noise measurements...
mm-Wave applications claim for accurate and reliable device models for their very high frequency operation range. This is not possible without any representative measurement of the intrinsic device performances especially HF small-signal measurements. In this paper we determine major parasitic contributions of regular HF test structures. Parasitic investigation goes from the probes down to the transistor...
In this paper we review a bit more than 10 years of SiGe BiCMOS technology development and present the best results published to date by the main contenders in the field. Next, with the support of recent results obtained at STMicroelectronics, we discuss the process optimization that led to further increase in the device operating speed. Finally, we present the characteristics of a 260GHz fT, 340GHz...
This paper presents a detailed investigation of the dual base method for intrinsic and extrinsic HBT's base resistance extraction that is of utmost importance for process monitoring and device modeling purpose. Ring emitter test structures layout, dc measurement conditions, and extraction methodology have been improved to get reliable results. A particular attention has been drawn to the external...
Based on different geometries of bipolar transistors, a new scalable method to determine the parasitic capacitances is presented. The total capacitance measured from cold S parameters could be split in an area junction capacitance, a peripheral junction capacitance and a constant oxide contribution. This method is applied to a ST state-of-art fully self aligned double poly BiCMOS technology, and results...
VDD reduction in advanced CMOS IC's push for reduced temperature stability spread of bipolar based BGR. To achieve this goal, a reliable extraction methodology for IC temperature coefficient is detailed. Based on corner lot measurements, a worst-case bipolar model is built. Bandgap circuit measurements are finally compared to statistical simulations.
For device modelling purposes, the geometry dependence of the external collector resistance has been investigated. Firstly, the collector resistance is split into a perfectly 1D vertical resistance and a 2D horizontal contribution. Using specific test structures and DC measurements, geometry independent parameters are then extracted. An analytical scalable formula based on Fourier techniques finally...
This paper presents the status of most advanced CMOS and BiCMOS technologies able to address very high-speed optical communications and millimeter-wave applications. The performance of active and passive devices available on bulk Si and high-resistivity SOI is reviewed and HF characteristics of state-of-the-art SiGe HBTs and MOSFETs are compared. The performance of building blocks designed in different...
This paper presents investigations led to simplify the collector module of SiGeC HBTs in order to reduce technology cost. Outcome of this work is an HBT featuring an all-implanted collector with record fT and fmax (>250 GHz)
A low-cost SiGeC HBT module for bulk and SOI RFCMOS platforms is described. The device features an all-implanted collector and a novel fragmented emitter layout, and requires 4 masks only. Record performances are demonstrated, with cut-off frequencies fT/f max as large as 230/240GHz and 140/200GHz on bulk and thin SOI substrates respectively
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