The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The inclusion of circuit-level blocks, such as ring oscillators, operational amplifiers and A/D or D/A converters, in technology characterization test chips is now a well-established practice. Such figure-of-merit (FoM) circuit blocks provide a means of judging technology performance and variability on-wafer during the technology development phase. In addition, FoM blocks are used to validate the...
The standard approach to generate the data required for automated proximity correction is to measure a set of patterned features using an optical tool or a critical dimension scanning electron microscope (CD-SEM). This paper describes the design of a set of on-mask electrical test structures to perform the same task which has a number of attractions. The electrical test structures are based on the...
The novel overlay test structure reported in this paper was purposely designed to serve as an application-specific reference material. It features standard frame-in-frame optical overlay targets embedded in electrical test features and fabricated by the same process as the parts being manufactured. Optical overlay is commonly used in process control applications due to its utility for determining...
With the highest ESD level in a smallest layout area, SCR device was used as effective on-chip ESD protection device in CMOS technology. In this paper, a waffle layout test structure of SCR is proposed to investigate the current spreading efficiency for ESD protection. The SCR in waffle layout structure has smaller parasitic capacitance under the same ESD robustness. With smaller parasitic capacitance,...
We developed parameter extraction method based on a BSIM3-like compact model to analyze low field drain current with size dependent mobility in nano-scaled MOSFETs. Our new straightforward algorithm has made it possible to automatically extract model parameters with high accuracy and robustness. It is applicable to wide variation of device sizes, structures and materials.
The integration of fully silicided gates on a high-k dielectric in a standard process flow offers a solid alternative to the conventional Poly/SiON devices. In this work, we provide an extensive analysis of the module yield extracted for such devices highlighting the need for specific additional alarm flags without which some integration problems might be overlooked. The impact at the circuit level...
A precise evaluation technique was created for developing magnetic random access memory (MRAM), especially memory that operates in a toggle-writing mode. This technique enables us to observe the detailed resistance transition of magnetic tunneling junction (MTJ) cells during complicated write operations. It was used to analyze failed cells and revealed that the MTJ characteristics in the third quadrant...
We propose and demonstrate a test chip for extraction of spatial and layout dependent variations in both transistor and interconnect structures. A scan chain approach is combined with low-leakage and low-variation switches, providing access to detailed analog device characteristics in large arrays of test devices. Compared to digital test structures such as ring oscillators, the test circuit enables...
We present a procedure for evaluating the accuracy and performance of critical dimension (CD) metrology tools used in monitoring the semiconductor manufacturing process. Our method involves a reference measurement instrument and SI traceable reference material to evaluate the accuracy and resolution of CD metrology tools. The achievable accuracy and intrinsic linearity of the tools under test are...
This paper presents a novel radio frequency (RF) structure for wafer acceptance test (WAT) to monitor RF device in the scribe line area with 60 mum or smaller in width. WAT including RF items for statistical analysis, yield enhancement and function verification is crucial for the success of system on chip (SoC). Conventional south-north GSG (C-GSG) structure, scribe line GSG (S-GSG) structure, which...
Power MOSFET's suffer from a strong self-heating effect. This phenomenon is currently modeled with a thermal resistance Rth. Understanding the evolution of the Rth with device scaling is today an important issue. This paper presents an improved test structure for temperature measurements in multifinger LDMOS power devices. This structure allows to access the temperature of every device finger. With...
A transmission line-based de-embedding technique for on-wafer S-parameter measurements is extended to the noise parameters of MOSFETs and HBTs. Since it accounts for the distributed effects of interconnect lines and for the pad-interconnect discontinuity, it is expected to yield more accurate results at high frequencies than existing approaches. Furthermore, by requiring only two transmission line...
In this paper, we report detailed studies on the impacts of sinter process and metal coverage on CMOS transistor matching and parameter variability in an analog CMOS technology. Transistor matching and parameter variations with different metal slotting sizes processed at different sinter temperatures have also been studied. It has been found that both metal plating and sinter temperature play critical...
The radiation hardness of advanced SiGe BiCMOS technologies is being evaluated in order to check their applicability for the front-end readout electronics of the ATLAS Upgrade in the framework of the Super-LHC at CERN. A model that describes the effect of ionizing radiation on bipolar transistors as an exponential term is widely accepted. Nevertheless, this model is not very precise in the bias ranges...
During the AC impedance characterization of devices, from the kHz-range up to the GHz-range, accuracy can be lost when a DC voltage is applied. Commercial high-voltage broadband bias-tees are often voltage-dependent, which can cause inaccuracies at low frequencies. A calibration technique with applied bias significantly improves the measurement accuracy. Additionally, a bias-tee has been developed...
This paper discusses a new technique developed for generating well defined RF large voltage swing signals for on wafer experiments. This technique can be employed for performing a broad range of different RF reliability experiments on one generic test structure. The frequency dependence of a gate-oxide wear out stress was investigated using this methodology for frequencies of up to 1 GHz.
A new methodology is proposed to extract self-heating free I-V curves, including the substrate current, of SOI MOSFETs based on triple-temperature, regular DC measurement. It is verified to be accurate with Hspice simulations and suitable for SPICE model parameter extraction. It is also demonstrated that extraction of self-heating free I-V curves is not only desired for efficient SPICE model generation,...
Recently, the PSP model was selected as the first surface-potential-based industry standard compact MOSFET model. This work presents the results of several qualitative "benchmark" tests that over the last two years were used to verify the physical behavior of the new model and its usefulness for future generations of CMOS IC design. These include newly developed tests and previously unavailable...
This paper describes the design and measurement of electrically measured test structures for the characterisation of dimensional mismatch in an advanced photomask making process. Test structures consisting of pairs of Kelvin connected bridge resistors have been fabricated on a chrome-on-quartz photomask plate. These have been electrically measured on-mask and the results used to obtain information...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.