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The quality level of mixed-signal ICs lags behind the below-part-per-million defect test escape rates of digital ICs, as a result of the traditional testing based on performance specifications. Methods increasing the controllability to solve the problem of the low fault coverage of analog and mixed-signal circuits are in practice limited due to the excessive area overhead they require and their impact...
This paper presents a technique for the fault-based test of the analog amplifiers. The circuit defects are modeled with the 2-fault transistor models. The test method combines the amplifier evaluation both in and out of the normal operating region, with the transconductance of the amplifier being the key test parameter. Furthermore, the additional low current test is employed in order to maximize...
An overview on the implementation of new physical effects into the heterojunction bipolar transistor compact model HICUM/L2 is presented along with a description of the quality testing procedures performed before its public release for production circuit design in commercial simulators. Related topics such as potential measures for model run time improvements and failures are also discussed. Significant...
While working with designers and DFT engineers in companies evaluating an “industrial-strength” analog fault simulator, it became apparent that intuition and theory often differ regarding random sampling of defects to simulate. This paper explores these differences. In one case, it was hoped that simulating more defects would increase the estimated coverage. In a second case, it was assumed that pre-simulation...
Now-a-days On-line testing becomes an indispensable part of DFT (design for testability) for detecting rapidly increasing intermittent faults in deep sub-micron ICs. Much of the proposed on-line testing techniques are for synchronous circuits as compared to asynchronous circuits. The existing online testing(OLT) techniques of asynchronous circuits involve development of checkers that verify the correctness...
The present work studies the response to an Analog Single Event Transient (ASET) of a Silicon-on-insulator (SOI) OTA. By adopting an ASET model previously reported and fully compatible with SPICE descriptions, a simulation campaign is carried out in the SOI OTA taken as case study. SOI technology happens to be well suited for radiation-hardened applications and is rapidly becoming a main-stream commercial...
A new method is presented to detect catastrophic defects from the signal analysis of dynamic current consumption waveforms of analog circuits. While other techniques use the whole information in a Root-Mean-Square computation or in black-box techniques such as a neural network, the central point of this work resides in the selection of waveform samples to create a signature able to discriminate a...
This paper presents a scalable electrical model for high-voltage laterally-diffused metal oxide semiconductor field effect transistor (HV-LDMOS) to determine the I–V characteristics, which can be used in SPICE simulators. This scalable model is represented as a hybrid model by computing its transfer function to enable its wide use in testing high-voltage devices. The scalable model has been validated...
The cost of integrated circuits increases with the complexity and integration density. This has led designers to consider testing from the design phase; that's what we call DFT (design for testability). In this paper, we propose a DFT solution, based on technique of IDDQ measuring current, by incorporating a Built-In Current sensor, whose function is to detect power consumption of different circuits...
In this paper, a test is developed for the Operational Transconductor (OTA). The technology used is the 90nm CMOS technology. The assumed fault model consists of six faults per transistor including the open-gate fault. It is proven that only two test values are enough to detect 34 of the possible 36 faults, i.e., a coverage of 94.4%. A Monte Carlo analysis is then performed to study the effect, on...
In earlier, Fault Analysis (FA) has been exploited for several aspects of analog and digital testing. These include, test development, Design for Test (DFT) schemes qualification, and fault grading. Higher quality fault analysis will reduce the number of defective chips that slip past the tests and end up in customer's systems. This is commonly referred to as defective parts per million (DPM) that...
In this paper, the issue of testing analog MOS current mode circuits for catastrophic open and short faults has been addressed. A case study based on the 6-transistor transconductor circuit is discussed. The five-fault model is assumed per transistor, namely a short circuit between any two terminals as well as an open-circuited drain or source. DC testing is performed in order to reduce test cost...
We present, implementation of a built-in current sensor (BICS) which takes into account the increased background current of defect-free circuits and the effects of process variation on ?IDDQ testing of CMOS data converters. A 12-bit digital-to-analog converter (DAC) is designed as the circuit under test (CUT). The BICS uses frequency as the output for fault detection in CUT. A fault is detected if...
In this work, we explore the ability of OBT for testing OTA-C filters with a more complex OTA configuration than in previously reported one. Adopting a second-order structure as a case study, we use a non-linear block in the feedback loop in order to force the oscillations. The evaluation of the test quality is made by fault simulation. The simulation results show that the filter present very good...
Just as digital design did 15 years ago; analog design has now readied a transition. The move to CMOS has made analog circuits more functionally complex, and that complexity leads naturally to functional errors in the designs, which in turn leads to respins and delays. And just as digital designers did 15 years ago, analog designers are beginning to realize that they need to employ a rigorous functional...
In this paper we investigate the effectiveness of iDDT-based testing in detecting resistive open defects for future CMOS technologies down to 22 nm taking into consideration the wide process variations associated with such technologies. The SPICE parameters that we use for such advanced models are taken from the predictive technology model (PTM) and the ranges of process variations are taken from...
In this paper we present a new technique called captureless delay testing points (CDTP). This technique allows the detection of delay faults left uncovered by launch-on-capture transitions, with top-off random launch-on-shift patterns that do not require fast switching scan enable signals. The CDTP random patterns are internally generated, requiring virtually no additional test time or memory tester...
Static power due to leakage current will become a major source of power consumption in the nanometer technology era. In this paper, we propose a simple yet effective technique to reduce both static and dynamic power consumption in the scan test process. The leakage current is restrained by selecting a good primary input vector to control the paths of leakage current during the scan shift process,...
The article presents a method of designing multiresonant ZVS boost converter including one transistor based on simulation testing. Dependencies are given between parameters of resonant circuit elements and parameters of the control system which condition ZVS operation of the converter. Results of simulation and experimental tests provide grounds for the conclusion that the presented method allows...
We propose a built-in scheme for generating all patterns of a given deterministic test set T. The scheme is based on grouping the columns of T, so that in each group of columns the number ri of unique representatives (row subvectors) as well as their product R over all such groups is kept at a minimum. The representatives of each group (segment) are then generated by a small finite state machine (FSM)...
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