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System-on-chip (SoC) is becoming a core technology in a growing range of consumer and other electronic devices. Cornerstones of SoC designs are analog and mixed signal (AMS) designs, which are integrated circuits required at the interfaces with the real world environment. To respond to certain challenges and due to the limitations of simulation techniques (long simulation runs, inaccurate results,...
Radio Frequency Identification (RFID) systems usage has seen a dramatic surge in recent years. The technology is pervasive and already pervades our daily lives from goods in retail stores, car tyres, through to car keys and medicine packaging. Increasingly RFID technology is being asked to do much more, for example in ePassports / identity Cards and in healthcare, which raises the stakes in terms...
This paper presents a 4 bit integer N CMOS programmable frequency divider with high speed and low power consumption. It is based on a dual-modulus prescaler, and programmable asynchronous and synchronous dividers. It works up to 3.4 GHz frequency clock. It is tested in PLL for 2.4 GHz band Zigbee standard. All results are taken from simulating extracted layout. It is implemented using Silterra 0.18...
In IC design flow, layout versus schematic (LVS) is a key step in layout verification phase, and writing the LVS rule file is considered a tough task that requires considering many details in order to give the verification tool the desired level of layout-understanding power. However, getting a hundred percent efficient rule file in the first shot is not likely to happen, therefore QA techniques on...
In this study we proposed a new method in order to reduce power dissipation in buses by eliminating cross-talk capacitances. The model is based on bus invert and forbidden pattern schemes and shows good efficiency and minimum overhead. A MATLAB program has been written to evaluate the proposed model and compare it with others.
We investigate the modeling of gate oxide shorts (GOS) in MOSFETs. We target channel-gate oxide shorts defects which are common shorts in today's MOSFETs and will become prevalent in future CMOS technologies. The proposed model for a defective MOSFET augments the defect-free model with three current sources. We test the validity of our model using HSPICE simulations, which show a good match in the...
Analytical formula for the resonance frequencies of circular, square, and hexagonal MEMS resonators are extracted based on the analytical model for extensional vibrations of MEMS resonators. Material properties for the MEMS resonators are then extracted based on the analytical formula. Experimental measurement is done to extract the material properties of single crystal silicon MEMS resonators to...
In this paper, a new method to implement any type of a chaotic generators is introduced by using field programmable gate array (FPGA). The aim of this method is to increase the frequency of the chaotic signals. The new method is based on MATLAB?? software, Xilinx system generator, Xilinx alliance tools, Leonardo spectrum or Synplicity Synplify and ModelSim XE PLUSE. The toolbox of the Xilinx system...
This paper presents a comparative study of field programmable gate array (FPGA) implementation of standard and truncated multipliers using very high speed integrated circuit hardware description language (VHDL). Truncated multiplier is a good candidate for digital signal processing (DSP) applications such as finite impulse response (FIR) and discrete cosine transform (DCT) etc. Significant reduction...
By scaling the technology, wiring has a big share of overall circuit capacitance and consumes a considerable part of dynamic energy. In digital circuits, buses become important part of wiring and their energy dissipation become comparable to the total circuit energy. So we are interested in lowering this energy, especially for low power and portable applications. On the other hand crosstalk noise...
The purpose of this work is to add one more circuit into the PLL to define the lock condition. New types of PLL lock detectors, the principles of their operation, parametrical comparisons are presented. Presented circuits provide a simple design and independence from supply voltage (analog lock detector) or design automation (fully digital lock detector).
This paper presents an electrical field sensor, which can be used in both biomedical applications and cell characterization. The lab-on-chip contains two main parts: (1) A CMOS lab-on-chip integrated circuit (IC) which is based on 0.18 ??m technology and includes the sensing and actuation parts, (2) a printed circuit board which contains the amplifications and conditioning parts. Experimental result...
This paper describes the field programmable gate array (FPGA) implementation of Rijndael algorithm based on a novel design of S-box built using reduced residue of prime numbers. The objective is to present an efficient hardware implementation of Rijndael using very high speed integrated circuit hardware description language (VHDL). The novel S-box look up table (LUT) entries forms a set of reduced...
A new operational floating current conveyor (OFCC) circuit is presented. The presented OFCC circuit is the first CMOS OFCC circuit which is suitable for low power VLSI applications. The proposed OFCC circuit is designed to achieve two design goals. The first designed circuit is a low power consumption OFCC circuit (LBW design) while the second design is a high bandwidth OFCC circuit (HBW design) with...
This paper describes the design of 2 GHz low noise amplifier using microwave integrated circuit (MIC) technique. The circuit was designed first to achieve maximum gain, then it designed to achieve the minimum noise, and finally some tradeoffs were done to get the minimum noise with the greatest available power gain. Also the sensitivity of the circuit with the variation of matching circuits at the...
In this work we present a novel MEMS interferometer based on the Mach-Zehnder (MZ) architecture. The interferometer is fabricated by deep reactive ion etching (DRIE) technology on an SOI wafer. The new structure is based on the use of two Si/Air beam splitters and two metallic mirrors, integrated with a comb drive actuator on a single die. The whole structure is integrated on one chip and no parts...
A need arises when using CAN buses to monitor the data on the bus as well as having the ability to inject further data onto it. This provides the ability to fully test a CAN network on both the frame level and the bit level. This paper introduces a new CAN bus analyzer and emulator. The proposed system on chip (SoC) is verified by simulation and implementation on FPGA board. Real time results show...
This paper presents an improved analysis for the intermodulation performance of the contact-type MEMS microswitches. Contrary to the previously published analysis, where the source voltage comprises two equal-amplitude sinusoids, in this paper the source voltage is a mutisinusoidal signal comprising 2N equal-amplitude equally-spaced sinusoids. Previously published results can, therefore, be obtained...
This paper presents a new category of MEMS variable capacitance devices which can provide a specific tuning range tailored to the specific application being considered. Depending on the tuning range chosen, this device can play the role of a variable capacitor, a switched capacitor, or a switch. The proposed structure can provide theoretical tuning ranges anywhere from 4.9 to 35 with a simple, yet...
This paper presents the system architecture of a primary mode oscillation loop of a MEMS GYRO interface. The loop is designed using an all digital PLL acting as a frequency selective gain element in the positive feedback oscillation loop. An amplitude control negative feedback loop is implemented to maintain the stability of oscillation amplitude and consequently the output reading scale factor. A...
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