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Presents the introductory welcome message from the conference proceedings. May include the conference officers' congratulations to all involved with the conference event and publication of the proceedings record.
Latest progress in microelectronics have enabled a new generation of low cost, low power, miniaturized, yet, smart sensor nodes. This new generation of wearable sensor nodes promise to deploy automated complex bio-signals analysis. In this paper, we present INYU, a wearable sensor device for physical and emotional health monitoring. The device obtains key vital signs of the user, namely Electrocardiogram...
We make the case that TDF timing tests, even when aggressively applied at-speed, uniquely detect mostly open defects within standard cells. The majority of these defects can also be detected at somewhat slower test speeds without the risk of unnecessary yield loss from test noise. Meanwhile, many other opens that can cause operational failures remain undetected by current LOC, and even LOS, TDF tests...
The growing usage of electronic systems in safety- and mission-critical applications, together with the increased susceptibility of electronic devices to faults arising during the operational phase mandate for the availability of effective solutions able to face the effects of these faults. When the target system includes a processor, one possible solution is based on running suitable test programs...
Simple and low cost method based on Built-in-Tuning (BIT) of passive filters in RFIC transceiver is presented, which is used to compensate for variability induced imperfections in RF subsystems. Auto-calibration of filter resistance values, based on Design-Of-Experiment (DOE) methodology, is proposed. This approach investigates process and temperature monitoring of the frequency band, the image-rejection-ratio...
The present work studies the response to an Analog Single Event Transient (ASET) of a Silicon-on-insulator (SOI) OTA. By adopting an ASET model previously reported and fully compatible with SPICE descriptions, a simulation campaign is carried out in the SOI OTA taken as case study. SOI technology happens to be well suited for radiation-hardened applications and is rapidly becoming a main-stream commercial...
In Serializer/Deserializer (SerDes) systems usually there is a mismatch between the devices used in the circuitry handling the two complimentary signals and the analog front-end equalizer (AFE) circuit. This introduces an unknown and relatively steady offset voltage into the differential signals, this offset affects the noise margin of the system. A design of selfcorrection offset amplifier based...
Charge pumping techniques are used to characterize and quantify the interface state densities in Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFET). When carried in a semiconductor production line, this technique needs to be time efficient, calling for automated testing environments. Moreover, the cost of the characterization equipment used in the test is always a factor of relevance for...
Circuit aging induced by the negative bias temperature instability (NBTI) has become a major factor of reliability. The NBTI-induced aging of a logic gate can be mitigated by gate replacement technique only when the input gates of a logic gate are of some specific types. A protectability-aware gate replacement technique is proposed in this paper to mitigate NBTI-induced circuit aging. In the proposed...
An operational tranconductance amplifier (OTA) is sized by applying multi-objective evolutionary algorithms. The OTA is designed using CMOS integrated circuit technology of 0.35 μm. From the obtained feasible solutions, a tolerance analysis is performed for each width (W) and length (L) of the MOSFETs. This analysis helps to evaluate the W/L tolerances of the transistors so that the developed optimization...
The Triple Modular Redundancy (TMR) strategy is a common and good option for a system to recover from possible faults. However, in case of a permanent fault in the TMR hardware, the redundancy advantage can be destroyed. In this paper, we present a low cost solution to enable Fault Detection, Isolation and Recovery (FDIR) in a TMR system. Our methodology uses the Assisted Design Flow (ADF) that implements...
Accurately estimating the failure region of rare events for nanoscale analog circuit blocks under process variations is a challenging task. In this paper, we propose a new statistical rare event analysis method. The new method is based on the iterative failure region locating scheme to reduce the sample counts while still maintains estimation accuracy. We derive the complete formulation for failure...
A way of improvement of an oscillator concept, dedicated to detection and tracking of low energy particles with low fluxes, is presented. The solution is based on an indirect detection of the current generated at the input of the detection chain, through a Voltage Controlled Oscillator (VCO) response. In order to improve the correlation between the input current and the oscillator response (signal...
This work analyzes a USB differential pair transmission line achieved in an inexpensive standard PCB laminate that is aimed for the Internet of Things ecosystem. An initial simulation in Sonnet EM simulator of the most basic structure is presented, along with a preliminary electromagnetics-based design as well as a basic EMC analysis under the IEC 61000-4-2 standard. In addition, the analysis of a...
A Controllable flip flop design for sequential synchronous systems is proposed. The flip-flop setup time and propagation delay is controlled with an additional setup time and delay control (SDC) input. With this SDC enable, it is possible to enhance the circuit timing performance when required. In this paper, it is shown that when the SDC input is enabled, the flipflop setup time and Clk-Q propagation...
In this paper a tolerance analysis in the electronic design of a simple chaos generator is reported. This simple chaotic oscillator is composed by four resistors, three capacitors and two opamps. A Verilog-A model for the opamps and capacitors is used herein. For the opamp, the model contains input impedance, finite bandwidth with a dominant pole and voltage saturation effects. In case of capacitor,...
A low-dropout (LDO) voltage regulator is optimized by evolutionary algorithms. Basically, tolerance analysis is performed alike a worst-case analysis within SPICE to rank the circuit elements presenting higher sensitivities, and according to the target specifications associated to two objectives, namely: Power Supply Rejection (PSR) and output capacitor value. The results from the tolerance analysis...
The most important step in the final testing of fabricated ASICs or the functional testing of ASIC and FPGA designs is the generation of a complete test set that is able to find the possible errors in the design. Automatic Test Pattern Generation (ATPG) is often done by fault simulation which is very time-consuming. Speed-ups in this process can be achieved by emulating the design on an FPGA and using...
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