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Advances in both semiconductor and automotive industry are today enabling the next generation of vehicles with significant electronics content than ever before. Consumers can now avail vehicle offerings in the form of Electric and Hybrid Electric Vehicles (EV/HEV) that have improved fuel efficiency, provide enhanced driver-passenger comfort and experience through Advance Driver Assistance Systems...
Advances in semiconductor device manufacturing technology, which have enabled reduced feature size and higher integration, have resulted in a gap between the defect level estimated at the design stage and that reported for fabricated devices. As one possible strategy to control test quality and cost, the authors have proposed weighted fault coverage estimation. In this study, we propose layout-aware,...
The quality level of mixed-signal ICs lags behind the below-part-per-million defect test escape rates of digital ICs, as a result of the traditional testing based on performance specifications. Methods increasing the controllability to solve the problem of the low fault coverage of analog and mixed-signal circuits are in practice limited due to the excessive area overhead they require and their impact...
Modern SOCs may be composed of hundreds of individual physical modules, referred to as tiles. The total number of scan channels servicing these tiles often greatly exceeds the number of SOC device pins available to connect those channels to test equipment. Traditional reliance on a small number of pin-to-channel test mode configurations, predetermined in hardware, results in inefficient scan data...
Diagnosing chain failures is extremely important to ramp up production yield. Use of modern day low pin compressors limit the observability making chain diagnosis a difficult problem. When multiple chains fail during initial ramp up of yield, the high-resolution patterns are generally used for diagnosis. These patterns are generated using special ATPG settings and are very high in numbers. These high-resolution...
The prevalence of bridging defects makes bridging fault models important to consider during fault simulation and test generation. The large number of bridging faults that can be defined for a circuit led to the development of procedures for selecting subsets of bridging faults that are likely to occur based on the circuit layout, and hard-to-detect bridging faults whose coverage provides a more effective...
There has been a growing trend in recent years to outsource various aspects of the semiconductor design and manufacturing flow to different parties spread across the globe. Such outsourcing increases the risk of adversaries adding malicious logic, referred to as hardware Trojans, to the original design. In this paper, we introduce a run-time hardware Trojan detection method for microprocessor cores...
This paper presents a complete on-chip ADC BIST solution based on a segmented stimulus error identification algorithm known as USER-SMILE. By adapting the algorithm for efficient hardware realization, the solution is implemented towards a 1Msps 12-bit SAR ADC on a 28nm CMOS automotive microcontroller. While sufficient test accuracy is demonstrated, the solution is further extended to correct linearity...
Prognostic diagnosis is desirable for commercial core router systems to ensure early failure prediction and fast error recovery. The effectiveness of prognostic diagnosis depends on whether anomalies can be accurately detected before a failure occurs. However, traditional anomaly detection techniques fail to detect “outliers” when the statistical properties of the monitored data change significantly...
In this paper, we present CORT, a factored concolic execution based methodology for high-level functional test generation. Our test generation effort is visualized as the systematic unraveling of the control-flow response of the design over multiple explorations. We begin by transforming the Register Transfer Level (RTL) source for the design into a high-performance C++ compiled functional simulator...
This paper shows new insights on the stochastic nature of aging-related timing impact in digital circuits. Varying critical paths through aging trigger the need for aging compensation control loop based on an unsupervised machine learning algorithm. Adaptive Resonance Theory (ART) algorithm is favored for its ability to handle the stability-plasticity dilemma.
Manual wafer-level die inking is a common procedure for excluding die locations that are likely to be defective. Although this is a more cost-effective process, as compared to the expensive burn-in tests, it remains a labor-intensive step during IC testing. For each manufactured wafer, test engineers have to visually inspect every failure map in order to identify any regions where additional die need...
This paper presents a methodology for reducing functional test time in subthreshold SoCs targeting ultra-low power (ULP) internet-of-things (IoT) devices. Due to their low operating speed and voltage, subthreshold SoCs require significantly longer time to test than traditional SoCs. The proposed method models trans-threshold correlations to allow high voltage, high speed testing while accurately predicting...
A functional safety solution based on multi-purpose built-in self-test and repair infrastructure for automotive SoCs is presented. This solution allows building a hierarchical network and managing it in multiple in-field test and repair modes.
Multilayer (3D) integrated circuit technology (3D chip technology) provides an attractive alternative to conventional circuit scaling methods, which rely solely on continued shrinking of device dimension. Chip stacking, through the use of through silicon vias (TSVs) and micro ball grid arrays or copper pillars, allows increasing chip complexity in a node independent way. 3D chip technology also opens...
Solid-state drives (SSDs) based on NAND flash memories provide an attractive storage solution as they are faster and less power hungry than traditional hard-disc drives (HDDs). Aggressive storage density improvements in flash memories enabled reductions of the cost per gigabit but also caused reliability degradations. A recent large-scale study revealed that the uncorrectable bit error rates (UBER)...
DRAM is a crucial component in computing systems, and is expected to be even more important as data-intensive applications become more prominent. A key challenge in advancing DRAM technology is the growing cost of refresh operations, which can impose a large impact on the energy efficiency of DRAM modules. Existing refresh mitigation techniques all require hardware modifications, which may be undesirable...
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