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Current carbon nanotube (CNT) synthesis processes are not perfect. One of the most critical issue is the presence of density variations in CNT growth. These variations are due to the lack of precise control of CNT location during the synthesis and the presence of metallic CNTs (m-CNTs). In this work we analyze the impact of CNT density fluctuations on carbon nanotube field effect transistor (CNFET)...
In this paper we present the results of the implementation of a nanoscale double-gate (DG) MOSFET compact model, which includes hydrodynamic transport model, in Verilog-A in order to carry out circuit simulation. The model in Verilog-A is used with the SMASH circuit simulator for the analysis of the DC and transient behavior electrical CMOS circuits. A template device representative for a downscaled...
In this paper the requirements and resulting costs for the digital hardware are discussed to steer a nonlinear interference suppression circuit (NIS). This NIS circuit suppresses a strong unwanted RF blocker by exploiting a nonlinear transfer function in a radio receiver. Nonlinear transfer functions enable frequency-independent amplitude discrimination because they do not obey to the principle of...
This work presents a straightforward approach to model the dynamic I–V characteristics of microwave FET transistors. Since the main cause of the transistor nonlinearity can be attributed to the drain-source current generator, its correct modeling is fundamental for predicting accurately the device behaviour under realistic operating conditions, namely large-signal operation. The experimental data...
A discussion about the LINC architecture with alternative views on the power combiner merged with the antenna, reduction of gain mismatch with less impact of PA output impedance and broadband behavior.
3T1D-DRAM cell has been stated as a valid alternative to be implemented as a L1 memory cache and substitute 6T-SRAM, highly affected by variability. While scaling down capacitor-less DRAM cells is a challenging trend, in this paper we show how it can be compensated the scaling drawbacks through the channel strain of the cell devices and the proposal of new cell configurations to further enhance the...
This paper presents some insights into the modeling of different Multi-Gate SOI MOSFET structures, and in particular Tri-Gate MOSFETs (TGFETs). For long-channel case an electrostatic model can be developed from the solution of the 2D Poisson's equation in the section perpendicular to the channel. allowing it to be incorporated in quasi-2D compact models. For short-channel devices a model can be derived...
Ballistic transport from low-field to high-field regime is reviewed with transition from low-field ballistic mobility to high-field drift velocity limited to the intrinsic velocity for a given dimensionality. Equilibrium Fermi-Dirac to Boltzmann to nonequilibrium Arora distribution is delineated and applied. Ballistic injection from the contacts is shown to be of paramount importance as channels scale...
The research related to micro- and nanoelectronics can be grouped in three main directions, i.e., More Moore, Beyond CMOS and More than Moore. For each of them some general trends and challenges are addressed. The convergence of the top-down technology, with bottom-up methods derived from fundamental disciplines such as materials physics, chemistry and biotechnology is opening a totally new world...
In the article we present a system for measurements of skin conductance and temperature of patient body. Presented system is a part of the recorder module of the MOnOff system. We propose an improved algorithm to measure of skin conductance and temperature, which reduces the power consumption of the measuring circuit. Construction of measurement circuits and practical experiments are presented.
In our investigation we focus on the A* Algorithm, which is widely used in the video games design theories. A* algorithm is the most common choice for solving the path-finding problems, because it's fairly flexible and can be used in a wide range of contexts. The main problem of A* Algorithm is the finite computer memory. When in need of finding a path on considerably large map, computer have to remember...
In this paper we present a novel approach to reduce the computation burden of a Field Programmable Gate Array based beamforming localization algorithm. This approach combines GCC (Generalize Cross Correlation) and DSB (Delay and Sum Beamforming). In this work, we reduce the position search spectrum by detecting the direction of arrival of the sound source before the computation of its position, this...
This paper deals with the investigation of the fault detection in separated parts of a mixed-signal integrated circuit example by implementing parametric test methods. The experimental Circuit Under Test (CUT) consisting of an 8-bit binary-weighted R-2R ladder D/A converter and additional on-chip test hardware was designed in a standard 0.35µm CMOS technology. For detection of catastrophic and parametric...
The cost of integrated circuits increases with the complexity and integration density. This has led designers to consider testing from the design phase; that's what we call DFT (design for testability). In this paper, we propose a DFT solution, based on technique of IDDQ measuring current, by incorporating a Built-In Current sensor, whose function is to detect power consumption of different circuits...
The paper deals with the parametric fault diagnosis of linear analog circuits in the frequency domain. The testability degree, which is referred to as the total number of testable network parameters, is theoretically independent of nominal values of network parameters, the set of test frequencies and the fault detection method. However, practical results show that the effective testability determined...
This paper introduces an optimization methodology for the design of RF varactors. The characterization of the varactor behaviour is supported by a set of equations based on technological parameters, granting the accuracy of the results, as well as the adaptability of the model to any technology. The varactor design is achieved through the implementation of a Genetic Algorithms (GA) optimization methodology,...
The machines used in High Energy Physics (HEP) experiments, such as accelerators or tokamaks, are sources of gamma and neutron radiation fields. The radiation has a negative influence on electronics and can lead to the incorrect functioning of complex control and diagnostic system designed for HEP machines. Therefore, in most cases the electronic equipments is installed in radiation-safe areas, but...
This paper presents the design methods that allow to drastically limit an area of a recording channel in multichannel integrated circuits dedicated to neurobiology experiments. The techniques that are presented in this paper allow to apply them in a 3D pixel multichannel integrated systems where area limitations are very strict. Furthermore, these allow one to minimize main problems e\ xisting in...
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