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From writing functional tests to managing design groups to managing major businesses, Dr. Rhines has been personally involved in the evolution of Design for Test. From this perspective, he will describe the driving forces and technologies that changed the way we design products to make them testable, and what will drive change in the future.
The Best Paper Award of ETS'13 goes to the paper entitled: "INFORMATION-THEORETIC SYNDROME AND ROOT-CAUSE ANALYSIS FOR GUIDING BOARD-LEVEL FAULT DIAGNOSIS" by Fangming YE (Duke University, US), Zhaobo ZHANG (Huawei Technologies, US), Krishnendu CHAKRABARTY (Duke University, US), and Xinli GU (Huawei Technologies, US). The award is formally handed over during the plenary opening session of...
This paper describes the fully automated GSS tool flow, which bridges the gap between Technology Computer Aided Design (TCAD) at the transistor level, and circuit simulations and verification. The purpose of the tool flow is twofold: (i) to allow rapid simulation-based Design-Technology Co-Optimisation (DTCO) and (ii) to allow generation of accurate compact models for Preliminary Design Kit (PDK)...
Timing errors are a major threat in modern integrated circuits. Suitable error tolerance design techniques exist, like Razor, aiming to confront with this situation. However, the silicon area cost of these solutions makes them unattractive for widespread use. In this paper, aiming to broaden the applicability of timing error tolerance techniques, we explore the ability to extend their use for low...
In this work we present a new scheme for the on-chip application of test patterns utilizing an accumulator structure whose inputs are driven by a barrel shifter. The consecutive patterns applied to the inputs of the Circuit Under Test differ in one bit, therefore the power consumed is lower compared to previously proposed accumulator-based pattern application schemes.
We propose a new property-checking-based LBIST architecture which uses hardware monitors to check certain properties in the output responses. If any property is violated, the failing property number is stored for diagnosis. The proposed architecture improves diagnosability considerably with minimal hardware overhead. Experimental results show that the diagnostic resolution achieved by our architecture...
Deterministic random bit generators can be used for cryptographic operations. An important feature of the DREG is collision resistance in order to avoid the generation of the same output sequence for different seeds. Further features are reverse calculation resistance and fault attack detection, which can in our design be reached by the COSSMA approach (COmplete Set of State MAchines) in combination...
A new method for logic simulation and fault modeling in combinational circuits with Structurally Synthesized BDDs (SSBDD) is proposed. The new model is constructed by merging different super-graphs (SSBDDs) related to different circuit outputs, which share as much as possible different subgraphs (SSBDDs) representing the circuit. We call this model as Shared SSBDDs (S3BDD) where each node represents...
The integration of more and more computing cores into processors drives the adoption of larger and larger Network-on-Chips (NoCs). Concurrently, the decreasing reliability of 1 the latest technologies promotes the utilization of fault-tolerant techniques. Unfortunately, the understanding of fault-tolerant NoCs is increasingly difficult as interconnect scale up, because they require the combination...
Analog checksum based fault tolerance for linear circuits has been proposed in the past but remains a theoretical artifact due to the high cost and complexity of error compensation while other redundancy based methods have prohibitive overheads. To resolve this, new low cost error compensation methods for widely used linear analog circuits are developed in this research. Trial and error based compensation...
Interposer is a critical component in a 2.5-D IC as it serves as a common platform upon which multiple known good dies are bonded. Any defect in an interposer will lead to a loss of compound yield. To avoid such a last-minute yield loss, we propose a timing-aware Built-In Self-Repair method to increase the fault tolerance of high-speed interposer wires. The most unique feature of our method as compared...
Decimal floating-point is a relatively recent addition to the IEEE standard (IEEE Std 754-2008). There exist few verification techniques that can check whether software libraries or hardware designs are in compliance with the standard. Our work presents a verification method to verify implementations of the decimal floating-point square root operation. We present an effective simulation based verification...
In response to reliability challenges of new systems being built, we are proposing a scalable Self-Test architecture for many-core processor systems. This BIST architecture periodically distributes test stimuli among identical processing cores in a many-core processor system, suspends normal operation of individual processing cores, applies test, detects faulty cores, and removes them from the system...
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