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We report a highly-sensitive plasmonic nano-ring transistor for monolithic terahertz (THz) active antenna. By designing an ultimate asymmetric transistor on a metal-gate structure, more enhanced (180 times) channel charge asymmetry has been obtained in comparison with a bar-type asymmetric transistor of our previous work. In addition, by exploiting ring-type transistor itself as a monolithic circular...
The area of flexible electronics is rapidly expanding and evolving. With applications requiring high speed and performance, ultra-thin silicon-based electronics has shown its prominence. However, the change in device response upon bending is a major concern. In absence of suitable analytical and design tool friendly model, the behavior under bent condition is hard to predict. This poses challenges...
In this paper, a closed-form physics-based surface potential approach is proposed to derive a compact model for current in high-frequency and high-power LDMOS transistors. For this purpose, we have modeled the drift region with three variable resistors. Effects of velocity saturation in the channel as well as the quasi-saturation due to the existence of the N-Drift region have been taken into account...
This paper presents the scope of applicability of Dual-Phase-Lag model in modern electronic structures. Moreover, the investigation of obligatory application of this model, instead of the classical approach based on Fourier-Kirchhoff model, to heat transfer modeling is included. Furthermore, the modified Fourier-Kirchhoff thermal model, containing the special time lag parameter, is also taken into...
This paper studies the design of standard CMOS two-stage operational amplifiers under power consumption and area constraints. The focus of the work is unity-gain bandwidth optimization, which is achieved by means of a procedure based on numerical analysis that allows determining the optimum sizing of op-amp transistors and the compensation capacitance as well as the best splitting of the allowed bias...
As the dimensions of electronic devices, especially transistors, are getting smaller and smaller, novel modeling approaches must be developed to reveal the physics and predict the performance of not-yet-fabricated ultra-scaled components. In this paper the basic requirements to simulate nanoscale devices are first reviewed before introducing a hierarchical quantum transport approach going from empirical...
This work investigates quantum ballistic transport in ultra-small junctionless semiconducting nanowire transistors, within the framework of self-consistent Schrodinger-Poisson problem. A sub-band decomposition approach has been taken to make the problem numerically tractable. Finally simulated transport characteristics for small diameter (d≤5 nm) n-Si-channel cylindrical gate-all-around junctionless...
This paper reports recent advances related to the piezoelectric oxide semiconductor field effect transistor (POS-FET) based touch sensing system research. We reported in past, the POSFETs with basic electronics realized on planar silicon substrates using CMOS technology. However, the planar POSFETs could not be used on 3D or curved surfaces such as the fingertip of a robot. To overcome this challenge...
Owing to the large increase number of transistors in the CMOS logic due to the unending demand for increase in speed of electronic devices and also low power consumptions, it is becoming difficult to incorporate all the small scaled transistors onto one single plane. Nanowire transistors are now been looked upon to mitigate this particular problem due to their small size and excellent gate control...
This work reveals the impact of quantum mechanical effects on the device performancce of n-type silicon nanowire transistors (NWT). Here we present results for two Si NWTs with circular and elliptical cross-section. Additionally we designed both devices to have identical cross-section in order to provide fair comparison. Also we extended our discussions by reporting devices with five different gate...
To investigate self-heating effects in double gate MOSFETs, a simulator solving self-consistently the Boltzmann transport equations (BTE) for both electrons and phonons has been developed. A Monte Carlo (MC) solver for electrons is coupled with a direct solver for the phonon transport. This method is particularly efficient to evaluate accurately the phonon emission and absorption spectra in both real...
The purpose of this paper is to analyze the ESD device electro-thermal behavior of BIMOS transistors integrated in ultrathin silicon film for 28 nm FDSOI UTBB high-k metal gate technology. This evaluation is based on 3D TCAD simulations with classical physical models using Average Current Slope (ACS) method and quasi-static DC stress (Average Voltage Slope (AVS) method). We show how the series resistance...
The capabilities of CP2K, a density-functional theory package and OMEN, a nano-device simulator, are combined to study transport phenomena from first-principles in unprecedentedly large nanostructures. Based on the Hamiltonian and overlap matrices generated by CP2K for a given system, OMEN solves the Schrödinger equation with open boundary conditions (OBCs) for all possible electron momenta and energies...
With the increasing density of transistors in advanced technology nodes, the radiation is an ongoing problem affecting the contents of memory cells. This paper presents the simulation results of radiation immunity for two different memory cell technologies: 32nm Bulk CMOS and 28nm FDSOI. The effect of Single-Event Upset (SEU) caused by the heavy ion impact with different Linear Energy Transfer characteristic...
An atomistic quantum transport simulator based on density functional theory is presented in this paper. It employs CP2K for the construction of the Hamiltonian and overlap matrices. The electron density and current in the conduction band is computed by solving a wave function equation using a sparse linear solver. To determine the open boundary conditions, a highly efficient extension of the parallel...
This article represents the results of mathematical modeling of thermocompensation scheme using bipolar junction transistor. Also it represents the result of temperature testing by experimental model in extended temperature range 25–2500C. It was shown that practical realization of this thermocompensation scheme is real for temperature up to 2500C and this method is capable of minimization temperature...
It is known that automated model generation (AMG) techniques are sufficiently mature to handle linear systems. Other AMG techniques have been working reasonably well for various levels of nonlinear behavior. However, most of the modeling are performed under MATLAB environment. To be more realistic, the models need to be translated into hardware description language (HDL) models, such as VHDL-AMS or...
In this paper, we propose a 2D numerical quantum simulator for silicon gate-all-around (GAA) nanowire transistors with cylindrical cross-section within the effective mass approximation. The Hamiltonian is expanded in the uncoupled mode space and the nonequilibrium Green's function (NEGF) formalism is adopted to calculate the electron density and current. An approximated isotropic effective mass is...
The reduction of the oxide thickness in advanced CMOS processes is one of the many advantages of technology downscaling, as it favors the reduction of the threshold voltage shifts due to radiation-induced gate oxide trapped charge. This inherent radiation hardness of deep submicron processes can be further exploited using gate-enclosed layout transistors with an annular design. In this paper we present...
In this paper we propose a new physically-based analytical model for junctionless transistors. Various MOSFET architectures based on single-gate (SG), double-gate (DG) and Gate-All-Around (GAA) transistors are studied. In particular the trade-off between the electrostatic control and the current drivability (first-order evaluation) is evaluated. Comparisons between numerical and analytical results...
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