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Employing a 8 band k.p solver, the self-consistent band structure of the rectangular IIIV nanowires (NW) has been calculated. It is shown that the strong confinement combined with the band nonparabolicity will considerably change the effective masses and the band gap. The mass tensor elements get heavier than the bulk values and improve the density of state (DOS) and centroid capacitance accordingly,...
Wafer level stacking of single crystal films enables 3D monolithic integration of electronic devices. The monolithic stacking technology based on Smart CutTM enables front end integration of large variety of devices with nanometer alignment capability; therefore it provides more degree of freedom for the designers and integration for high density and better performance. Several applications can fully...
Random Telegraph Noise (RTN) has become dominant with transistor rapid scaling in recent years. We simulate RTN-induced frequency fluctuation of Ring Oscillators (ROs) using a circuit-level simulator to replicate measurement results from previous works. Consequently, we can predict dependences of frequency fluctuation on operating voltages, number of ROs stages, gate widths, and body biases.
Stochastic device degradation — due to individual oxide defects — like Random Telegraph Noise (RTN) and Bias Temperature Instability (BTI) causes a threshold voltage drift of transistors resulting in decreased SRAM yield and performance. BTI and RTN has been shown to follow an defect-centric behavior, which can be bimodal in nature for heterogeneous gate oxide stacks. Consequently the tail of the...
We have evaluated the impact on the reliability of an innovative process flow, specifically designed for peripheral MOSFETs of DRAM memories. Al and MgO layers are deposited, diffused into the gate stacks of NMOS and PMOS and finally removed. We have demonstrated an anomalous yet predictable PBTI behavior, coupled with a more standard NBTI one. Decent lifetime is achieved for both gate stacks, demonstrating...
In this paper, we present a standard cell design methodology for Spin Wave Device (SWD) circuits. We perform Place and Route (P&R) experiments against a 10nm FinFET CMOS technology and compare the area, the routing and metal distribution of several arithmetic benchmarks. We show that SWD circuits although they require more metal layers than CMOS designs and although they contain double the number...
This paper reports the positive bias temperature instability (PBTI) characteristics for n-type fin-channel tunnel field-effect transistors (TFETs) with high-k gate stacks. The subthreshold slope (SS) is not degraded at all while the threshold voltage (Vth) shifts in the positive direction by the PBTI stress. The activation energy of ΔVth for TFETs is almost the same as FinFETs, indicating that the...
The singled-out purpose of electrostatic discharge (ESD) devices is that these devices should protect electronic circuitry against fast-transient voltage/current spikes. Although the overall signal variation occurs within a nanosecond, the corresponding currents can ramp up to a multi-Ampere level. Fast varying current patterns give rise to equally fast varying induced magnetic fields being proportional...
To clarify the design guide of single-inductor multiple-output (SIMO) buck converters in discontinuous conduction mode (DCM) targeted for small-size and low-power IoT applications, equations of optimal design parameters (transistor size, inductance, and switching frequency) to maximize the power conversion efficiency are derived for the first time. The analytical optimal designs are verified with...
This paper makes a review of main methods to improve the linearity of ADCs. Methods are collected in view of mainstream techniques. A model of redundant noise-shaping Pipelined Flash-SAR ADC is proposed, which is the combination of Flash, Pipeline, SAR and ΣΔ ADC, the effectiveness of the model is demonstrated by simulation. Also, application of dynamic element matching (DEM) linearization techniques...
We demonstrate experimentally and theoretically the existence of circuit-layout-dependent low-k damage by plasma radiation. Circuit-layout-dependent low-k damage apparently occurs in nitrogen (N2) plasma, not in argon (Ar) plasma. Using an electromagnetic simulation and the dispersion analysis, we reveal that E-field in the low-k film is enhanced for specific Cu-line layouts in the case of N2 plasma...
Deep trench isolation (DTI) with “walkout” onset tunneling voltage (Vonset) can cause serious confusion for performance enhancement and process optimization in technology development. The ordinary breakdown voltage (BV) “walkout” phenomenon occurs when a premature avalanche breakdown injects high energy carriers into an oxide so that subsequent stress may causes an increase in oxide breakdown voltage...
Not only PVT detection techniques but also a leakage compensation design are proposed to carry out 650/500 MHz 2×VDD output buffer in this paper. The proposed 2×VDD output buffer contains a novel PVTL (Process, Voltage, Temperature, Leakage) compensation circuit to resolve the problems in output buffers of nano-scale CMOS technologies. Particularly, the leakage compensation design is realized by an...
High speed TSV signals can penetrate through the dielectric liner material, transfer in the silicon substrate and degrade the performance of FEOL devices. In this paper we investigate TSV noise coupling to active device including both FinFET and planar transistors. Calibrated TCAD models are used to perform time domain analysis and understand the mechanisms of substrate noise interaction with active...
Dual Rail SRAMs are widely used to enable Dynamic Voltage and Frequency Scaling (DVFS) in SRAMs where array voltage cannot be scaled down. DVFS operating points are limited by maximum differential supported between two supplies of the SRAM. To extend gains of DVFS, we propose a Low Standby Power — Capacitively Coupled Sense Amplifier (LSTP-C2SA) that enables further lowering of periphery supply in...
In this work, the potential of Si1−xGex Quantum Wells (SiGe QW) for future DRAM periphery transistors and more generally for Low Power applications is investigated. It is shown that an increase of Ge content in the channel leads to a significant reduction of threshold voltage and to an increase of long channel mobility. However, an increase of external resistance is observed for Si1−xGex Quantum Well...
In this paper, the performances of a lateral thin-film PIN photodiode based on silicon-on-insulator technology are reported for applications from blue to red wavelengths. The platform consists of a micro-hotplate with a suspended heater and a photodiode. Responsivities of 0.01 to 0.05 A/W were obtained for 450–900 nm light range in reverse bias operation. Suspended photodiodes give up to 5x responsivity...
In this paper, we investigate the hybrid TFET-FinFET 32-bit carry-look-ahead adder (CLA) circuit and compare the delay, power and power-delay product (PDP) with all FinFET and all TFET implementations in near-threshold region. We use atomistic 3D TCAD mixed-mode simulations for transistor characteristics and HSPICE circuit simulations with look-up table based Verilog-A models calibrated with TCAD...
A low Vmin, 6T-SRAM is realized in 28nm FDSOI technology using read and write assist methods. We could reduce the Vmin of SRAM cell to 0.52V for the 0.120um2 high density 6T-SRAM. Reduced read margin of the SRAM cell is recovered using a transient rise in cell supply level through word-line coupling. Write assist is realized using application of PVT selective negative bit-line approach. Bit-line is...
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