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The silicon MOS transistors for VLSI have been scaled down for more than forty years in order to attain higher speed, lower power, higher integration, and lower cost. The gate length is now less than 30 nm. The silicon devices are certainly in the nanometer regime. Fig. 1 shows technology nodes and gate length according to ITRS [1]. It is predicted in the 2009 version of ITRS that the gate length...
In this paper research on nano-carbon structures for applications beyond CMOS devices is reviewed. Progress in the synthesis, processing and integration of ultra-thin conducting carbon films, graphene and nanotubes for applications such as interconnects, transistors, spintronics and sensing are critically reviewed. This paper present a comprehensive study on large scale CVD grown graphene films and...
ZnO nanowire devices were fabricated from top-down using optical lithography. The nanowires are formed from anisotropic etch of 100 nm Filtered Cathodic Vacuum Arc (FCVA) deposited ZnO thin film. The nanowires are characterized using SEM and Raman spectroscopy via image mapping. The current-voltage characteristics showed a typical ohmic behaviour after contact annealing, reflecting the influence of...
Combined measurements of random telegraph noise of drain current and drain current - gate voltage characteristic are employed for determination of field-effect charge carrier mobility in surface channel of nanowire inversion mode and accumulation mode MOSFETs with taking into account parasitic source-drain resistance.
First-principles electronic structure methods are used to predict the rate of n-type carrier scattering due to phonons in highly-strained Ge. We show that strains achievable in nanoscale structures, where Ge becomes a direct band-gap semiconductor, cause the phonon-limited mobility to be enhanced by hundreds of times that of unstrained Ge, and over a thousand times that of Si.
We have simulated silicon nanowire junctionless transistors with a 3 nm gate length within a Density Functional Theory (DFT) framework. We explored the response of transistors to source-drain bias, VDS, and gate voltage, Vg. Also, the effect of bulk and surface adatom in the wire cross section was evaluated.
In this paper we investigate the performance of short channel junctionless gate-all-around (GAA) transistors, by comparing the I_V characteristics, subthreshold swing and drain-induced barrier lowering (DIBL) of junctionless GAA transistors with accumulation-mode GAA transistors. We also compare the I_V characteristics of junctionless GAA transistors for different wafer and transport orientations...
Schottky diode structures with Ge quantum dots (QDs) have been grown by Molecular Beam Epitaxy (MBE). They have been employed to fabricate NiSi Schottky diodes with Ge dots buried below the metal-semiconductor junctions. These diodes have cut-off frequencies up to 1.1 THz (calculated from S-parameter measurements up to 110GHz). Preliminary results demonstrating the implementation of Ge QD Schottky...
This work presents a process to fabricate FinFETs in bulk silicon with advancements in critical fabrication steps such as STI trench oxide recess and adjustment of fin height. These steps are accomplished with the adoption of Siconi™ Selective Material Removal (SMR™) in the fabrication flow. FinFETs obtained with this new integration scheme were tested in a co-fabrication process flow proposed to...
A simple analytic model for the progressive breakdown (BD) dynamics of ultrathin) gate oxides is presented. It is shown how the interplay between series and parallel resistances that represent the breakdown path and its surroundings leads to a sigmoidal I-t characteristic compatible with experimental data. The analysis is carried out using the Lyapunov exponent and the potential function associated...
We have simulated silicon nanowire junctionless transistors with a 3 nm gate length within a Density Functional Theory (DFT) framework. We explored the response of transistors to source-drain bias, VDS, and gate voltage, Vg. Also, the effect of bulk and surface adatom in the wire cross section was evaluated.
Random telegraph noise (RTN) in bulk and fully depleted (FD) SOI MOSFETs are measured by device matrix array (DMA) TEG for statistical analysis. It is found that, in the tail part of the distribution, threshold voltage change by RTN (ΔVth) in FD SOI MOSFETs is smaller than that in Bulk MOSFETs. 3D device simulation confirms that ΔVth becomes very large in bulk MOSFETs when a trap happens to be in...
Gadolinium-silicate (GdSiO) as high-k dielectric in sub 10nm gate first nanowire (NW) nMOSFETs is investigated. NW- and UTB- nMOSFETs with conventional SiO2/Poly-Si gate stacks have been fabricated and compared with GdSiO/TiN NW nMOSFETs. Specific nMOSFETs with multiple NWs in parallel have been used to extract the effective mobility by split-CV method and to eliminate the series resistance to correct...
We have carried out 3D Non-Equilibrium Green Function simulations of a junctionless gate-all-around n-type silicon nanowire transistor of 4.2 × 4.2 nm2 cross-section. We model the dopants in a fully atomistic way. The dopant distributions are randomly generated following an average doping concentration of 1020 cm-3. Elastic and inelastic Phonon scattering is considered in our simulation. Considering...
We investigate the properties of ballistic spin field-effect transistors (SpinFETs). First we show that the amplitude of the tunneling magnetoresistance oscillations decreases dramatically with increasing temperature in SpinFETs with the semiconductor channel made of InAs. We also demonstrate that the [100] orientation of the silicon fin is preferred for practical realizations of silicon SpinFETs...
In this paper, we for the first time demonstrate a detailed radio frequency (RF) simulation study of the novel planar-type body-connected FinFET with 45 nm gate length, for which the DC behavior exhibits better ION-IOFF current ratio and improved transconductance performance when compared with a planar-type FinFET. The RF characteristics are carried out as functions of gate voltage (VG) and drain...
The chemical reactions at the higher-k LaLuO3/Ti1NX/poly-Si gate stack interfaces are studied after high temperature treatment. A Ti-rich TiN metal layer degrades the gate stack performance after high temperature annealing. The gate stack containing TiN/LaLuO3 with a near stoichiometric TiN layer is stable during 1000 °C, 5s anneals. Both electrical and structural characterization methods are employed...
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