The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
An approach towards a high speed current mode SAR ADC is presented. Even though SAR ADCs based on charge redistribution have been significantly improved in efficiency and operating frequency, they are still limited by the settling requirements of the switched capacitor DAC. To overcome this limitation, we propose the use of a current mode SAR ADC incorporating a current steering DAC operating at 2...
In this paper a method to reduce the harmonic distortion caused by the switching operation in switched-R-MOSFET-C filters is presented. The technique is demonstrated through simulations and backed by analytical expressions for first order active RC and second order biquad filters; the improvement in clock distortion is presented and compared with previously reported architectures. The proposed harmonic...
Nanoscale VLSI systems are subject to an ever increasing performance variability, which hinders performance scaling and increases verification complexity. In this paper, we study an often neglected source of performance variability, namely logic inputs or system workload. We present input-aware statistical timing analysis, which gives not only critical path delays but also critical path activating...
This paper proposes a new macromodel that takes into account the threshold switching and the resistance recovery processes in addition to the drift behavior of a Phase Change Memory (PCM). Simulation results are provided for both DC and drift behaviors; they show that the proposed macromodel is very accurate at a small error when compared with data from experimental devices. A sensitivity analysis...
The increasing integration of analog/mixed-signal (AMS) circuits into system designs has further complicated an already difficult verification problem. Recently, formal verification, which has been successful in the purely digital domain, has made some in-roads in the AMS domain. This paper describes one such formal verification tool for AMS circuits, LEMA. In particular, LEMA is capable of generating...
Neural spike detection is an important step in understanding neurological activities. The spike firing rate which could be rapidly changing in the recording experiment would make noise estimation inaccurate thus compromises the spike detection performance. In this paper, we propose a new noise estimation method for neural spike detection. Different from the traditional methods that deal with all the...
The hippocampus is widely studied with neuroimaging techniques given its importance in learning and memory and its potential as a biomarker for brain disorders such as Alzheimer's disease and epilepsy. However, its complex folding anatomy often presents analytical challenges. In particular, the critical hippocampal subfield information is usually ignored by hippocampal registration in detailed morphometric...
In this work, we investigate the problem of estimating time-varying noise distribution parameter on a factor graph. A new message passing scheme is proposed by incorporating the variational Bayes (VB) into the belief propagation algorithm for estimating of time-varying noise distribution parameter in a low-density parity-check decoder. The scheme can also be used for the estimation of the correlation...
This paper presents the design of a monolithic low power CMOS low-noise instrumentation amplifier (INA) for low-power biosensor applications. To achieve high-fidelity cardiac signal acquisition, the INA circuit and system design requirements are discussed. Design strategies for mitigating the in-band flicker noise and thermal noise using chopper-stabilization and current scaling techniques are investigated...
This work addresses the problem of wafer-to-wafer matching algorithm for 3D integration of ICs. One critical limitation of the traditional wafer matching methods is that they have attempted to maximize the number of resulting 3D ICs with no faulty (bad) die, but never took into account the time variation between the individual dies in a 3D integrated chip. We show that without considering time variation...
An efficient and accurate sensitivity based methodology is introduced for modeling reactive ion etch (RIE) in BEOL 2.5D parasitic extraction. Proposed methodology involves calibration of analytical equations based on layout parameters that are fitted to capacitance and sensitivity data from 2D field solver. Formulas are derived along with new capacitance and sensitivity equations in a 2.5D parasitic...
Soft errors have become one of the most challenging issues that impact the reliability of modern microelectronic systems at terrestrial altitudes. A new methodology to abstract, model, and analyze Single Event Transient (SET) propagation at different abstraction levels (transistor and gate level) is proposed. Transistor level characterization libraries are developed to abstract the impact of input...
A novel method of doing co-ordinate transformation for LC/van der pol(vdp) oscillator is proposed. It allows vdp to be solved as a conservative system by applying Hamiltonian formulation using calculus of variation. The procedure is developed to calculate the constant of integration, a generalized concept of energy. Such constant of integration, which is different from energy, has implication on the...
In this paper, a CMOS neural amplifier based on memcapacitor has been realized. A memcapacitor is a new element based on memristor. A performance comparison between memcapacitor based realization and conventional integrated one has been introduced. The circuits were simulated using 90nm CMOS technology, Vdd = 1.2v, for a total input referred noise of 1.97 µVrms and a total power consumption of 1.28...
The Readout Integrated Circuit (ROIC) consists of charge integration, charge to voltage conversion, Pixel voltage multiplexing, signal transfer and amplification stage. The control circuit manages all the sequential events from charge integration to amplification stage. The large dynamic range requirement is the most challenging aspect in modern CMOS process. The infrared (IR) detectors looks for...
Coarse Grained Reconfigurable Architectures (CGRAs) are promising platform based on its high-performance and low cost. Researchers have developed efficient compilers for mapping compute-intensive applications on CGRA using modulo scheduling. In order to generate loop kernel, every stage of kernel are forced to have the same execution time which is determined by the critical PE. Hence non-critical...
Comparative study between the proposed technique and MATLAB-built-in deconvolution-functions with regard to deconvolution errors is discussed, which have a crucial impact in reversing the effects of convolution with Random Telegraph Noise (RTN) and Random Dopant Fluctuation (RDF) on overall SRAM margin variations. The proposed algorithm successfully avoids noise amplification thanks to eliminating...
3-D ICs provide more logic space by introducing a multiple tier structure. Through silicon vias (TSVs) are utilized for signal propagation between multiple tiers. However, TSVs are vulnerable to fracture, which leads to lower yield. This paper analyzes different yield aware TSV redundancy techniques from a hardware overhead and effective redundancy perspective. A set of mathematical relationships...
Conventional analog Pulse-Width-Modulation (PWM) Class D Amplifiers (CDAs) require analog input signals that are typically provided by a Digital-to-Analog Converter (DAC). A PWM-in PWM-out CDA, on the contrary, is able to receive digital PWM signals as its input signals, hence not requiring said DAC as the ‘interface’ to digital signal processing circuits. In this paper, we analytically investigate...
A digital-to-transcoductance converter is presented for use with digitally programmable Nauta structure operational amplifiers. The converter architecture consists of parallel connected tri-state CMOS inverters sized in such a way as to present a complete range of transconductance tunability at the expense of linearity and transconductance output range. Our converter architecture is analysed under...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.