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Device, interconnect scaling and interconnection bottleneck are among the major challenges for CMOS scaling. Furhtermore, signal integrity issues like crosstalk-leakage of charge between capacitively coupled nets among neighboring signal lines-is becoming inexorable. We propose to astutely turn this detrimental effect into an advantage by engineering the interference among signal lines. Our proposal...
In this work a model of the oscillator with inductive coupling of the gates operating at ultralow voltage is presented and experimentally verified. The topology needs a bias voltage at the gates, and we propose a circuit called starting block to generate this voltage from the supply. Theoretical behavior is compared with experimental results, showing good agreement. The circuit, which behaves as astable...
Lateral GaN-on-Si HEMT technology enables integrated high-voltage half-bridges with gate drivers. However, the capacitive coupling through a common conductive substrate influences switching characteristics. The measured hard-switching turn-on time with floating substrate increased to over 16 ns as compared to conventional source-connected substrate (1 ns), switching 300 V/4A with GaN ICs comprising...
We demonstrate that FDSOI transistors co-integrated with a diode implemented below the buried oxide (BOX) become strongly sensitive to visible light. The carriers photogenerated in the diode create a Light-Induced Vt Shift (LIVS) in both NFET & PFET transistors by means of capacitive coupling, without direct electrical connection between the photodiode and the sensing transistor. This optical...
Important characteristic of any VLSI circuit isits power consumption, reliability, operating speed and siliconarea. Dynamic CMOS designs provide high operating speedscompared to static CMOS designs combined with low siliconarea requirements. Pipelines can be used for achieving highcircuit operating speeds. However, as the operating frequencyincreases, the number of pipeline stages should also increaseand...
In the pursuit for building hardware accelerators to compute optimization problems researchers realize that the challenges in achieving this objective lie not only in implementing the hardware but also in the formulating the computing fundamentals of such designs. Neural network algorithms are considered most suited for this task, as there is usually a direct description of distributed computing entities,...
A level-shifting circuit with sub-nano-second propagation delay for high input voltage switched-mode power converters is presented. The proposed circuit uses isolated low-voltage NMOS transistors and capacitive coupling to shift the control signal of the high-side power switch from a low-voltage logic domain (VLogic ∼ 5V) up to a high-voltage power domain (VIN ∼ 65V) with less than 115ps propagation...
A neuron-MOS-based dynamic circuit scheme with two-phase clocks for realizing voltage-mode quaternary logic, is proposed. The dynamic quaternary inverter and literal circuits are designed, and the standard CMOS process with a 2-ploy layer is adopted without any modification of the thresholds. In the proposed circuits, the problem of floating output nodes is solved. The proposed circuits have some...
This paper proposes a modified differential Colpitts CMOS VCO for mm-wave applications requiring wide tuning range, mW output power levels and low DC power consumption. This VCO achieves a large tuning range of 8.6 GHz between 93.9 – 102.5 GHz by using switched magnetic coupling at the gate inductor. Continuous frequency tuning is achieved by controlling the transistor gate capacitance with its bias...
We present a physically grounded modeling, simulation, and parameter-extraction framework that targets design and engineering of ultra-scaled devices and next-generation channel materials. The framework consists of a fast and accurate Schrödinger-Poisson solver/mobility extractor coupled to a device simulator. The framework brings physical modeling of semiconductor channels to device design and engineering...
We report the cryogenic-temperature electrical measurements of a planar silicon metal-oxide-semiconductor (MOS) based single hole transistor. A multi-layer gate electrode architecture allows independent control of hole densities in the leads and quantum dot. Stable Coulomb blockade oscillations are observed over a large range with minimal hysteresis. Separate tunability of the tunneling barrier enables...
Dynamic circuits using n-channel multiple-input floating-gate MOS(FGMOS) transistors to realize binary and ternary logic are presented. In binary domino circuits, the n-channel FGMOS transistors are used to replace the nMOS logic block to simplify the circuit structure. By using the advantage that voltage signals are easy to be added by means of floating gate in multiple-input FGMOS transistor, a...
For flash memory devices the thicknesses of the control and tunneling oxides in the floating gate transistor (FGT) are crtical parameters. We recently proposed a floating gate transstor using multilayer graphene nanoribbon (MLGNR) and carbon nanotube (CNT). In this paper, we have analyzed the impacts of scaling the thickness of the control and tunneling oxides in the proposed MLGNR/CNT based FGT....
A No Race (NORA) dynamic logic using neuron-MOS transistor is presented. The circuit is designed using the n-channel neuron-MOS transistor instead of the nMOS logic block or pMOS logic block in the conventional NORA dynamic logic circuit. The proposed full-adder shows that the logic block of NORA circuit can be simplified by utilizing neuron-MOS transistor. A simple synthesis technique of the n-channel...
A new family of two stage op-amps with broadband open loop response is introduced. These have a significant reduction of the DC open loop gain and maintain a high gain at frequencies as low as 1 Hz. This provides them with low DC offset. The proposed circuits are based on the Quasi-Floating Gate (QFG) technique, using a novel implementation for active loads that provides a very low effective resistance...
This study presents an experimental analysis of the Xray radiation effect on the drain induced barrier lowering (OIBL) of strained and unstrained, p and n type triple gate SOI MuGFETs. In both types of devices, the narrow fin transistors are more immune to radiation because of the better coupling among the gates. It is shown that total dose damage in nMuGFETs always leads to a performance degradation,...
In this paper, a new positive feedback source-coupled logic (PFSCL) style with higher speed than the existing PFSCL style is proposed. The proposed logic style replaces the load in existing PFSCL with a new load which exhibits capacitive coupling that enhances the switching speed of the circuits. The mechanism of capacitive coupling is modeled and its effect on the propagation delay is described....
A new quadrature voltage-controlled oscillator (QVCO) topology is proposed which consists of two same traditional low voltage-controlled oscillator and it is achieved by using back-gates coupling. The use of back-gates makes quadrature output clocks of voltage-controlled oscillator, reduces power dissipation and phase noise. That connecting the output terminal to the body terminal through resistor...
We propose an original architecture adapted to the 10nm transistor node (pitch 64nm) for FDSOI technology. This structure features self-aligned contacts and a gate capping dielectric layer preventing any short in case of lithographic misalignment of contacts. 2D simulations are carried out to quantify parasitic capacitances. Technological solutions are then proposed to optmimize this key parameter...
Graphene is a promising candidate for future electronics such as RF transistors, interconnects and flexible components. The simulation and analysis of graphene transistors (GFETs) has so far relied on two approaches: on one hand, compact modeling is efficient but tends to lack physical details and neglects geometric phenomena such as fringing electric fields. On the other hand, atomistic simulations...
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