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The challenges of the Internet of Things (IoT) in an urban environment are driven by smart vehicles which need to be able to efficiently sense and communicate with other nearby vehicles. System-on-chip (SoC) applications in the automotive market have strict circuit performances and reliability requirements for a temperature range of up to 175 0C. This work proposes an analysis of latched-comparators...
This paper presents a wideband CMOS FDSOI fully-balanced analog multiplier which is part of a magnitude calculator for real-time spectrum sensing. Simulations based on a 28nm CMOS FDSOI technology show that the proposed multiplier offers 13.8GHz bandwidth when loaded by a high capacitance with a power consumption of 343mW under a IV supply. Multiplication between high frequency voltage samples satisfy...
Internet of Things (IoT) is a topic of growing interest and intensive research in industry, technological centers and academy, where data communication is one of its most relevant aspects. Since IoT is an open field for new applications, it does not have yet a standard communication protocol. This paper presents the system level design of a WiFi receiver supporting the novel low power standard IEEE...
Detecting local light incident angle is a desirable feature for CMOS image sensors for 3D image reconstruction purposes. Advances in the CMOS technologies in the last years have enabled integrated solutions to perform such a job. However, it is still not viable to implement such a feature in regular CMOS image sensors due to the great number of pixels in a cluster to perform incident angle detection...
In this work a model of the oscillator with inductive coupling of the gates operating at ultralow voltage is presented and experimentally verified. The topology needs a bias voltage at the gates, and we propose a circuit called starting block to generate this voltage from the supply. Theoretical behavior is compared with experimental results, showing good agreement. The circuit, which behaves as astable...
The HEVC standard is one of the newest video coding standards developed to face the upcoming challenges concerning video processing. HEVC allows only one type of entropy encoder, which is the CABAC (Context Adaptive Binary Arithmetic Coding), responsible for the symbolic data representation in order to translate the final video bitstream to a smaller number of bits. This work presents hardware architecture...
This work presents a low-area scalable architecture for the Depth Modelling Mode 1 (DMM-1) encoder of the 3D High Efficiency Video Coding (3D-HEVC) standard, removing the refinement stage. This simplification causes a small BD-rate increase (0.09%) but a significant reduction in memory usage of 30%. The scalable architecture can support different block sizes. Synthesis results for ST 65 nm Standard...
The demand for higher quality video has increased in the past few years, due to the huge amount of electronic devices that process digital video in even higher resolutions. For that purpose, video coding techniques are used, which have, as main goal, the reduction of the required representation to process a digital video. Furthermore, embedded hardware video solutions are sought for both industry...
The HEVC is one of the most recent video coding standards, developed in order to face upcoming challenges, due to higher video quality and resolution. One of the HEVC components is the entropy encoder, which consists only of the Context Adaptive Binary Arithmetic Coding (CABAC) algorithm. The CABAC algorithm imposes some severe difficulties in order to achieve increasing throughput, due to the high...
Stereo matching systems that generate dense, accurate, robust and real-time disparity maps are quite attractive for a variety of applications. Most of the existing stereo matching systems that fulfill to all of these requirements adopt the Semi-Global Matching (SOM) technique. This work proposes a scalable architecture based on a systolic array, fully pipeline. The design builds on a combination of...
This work proposes a secure Network-on-Chip (NoC) approach, which enforces the encapsulation of sensitive traffic inside the asymmetrical security zones while using minimal and non-minimal paths. The NoC routing guarantees that the sensitive traffic communicates only through trusted nodes, which belong to a security zone. As the shape of the zones may change during operation, the sensitive traffic...
Many-core architectures are similar to a computer network, where it is necessary to ensure the security during the execution of sensitive applications. This article discusses two security-related issues: the secure admission of applications and the prevention of resource sharing during their execution. The safe application admission is an open research subject for many-core systems. Although several...
Digital circuit technologies at nanoscale levels increase the likelihood of permanent, transient and intermittent faults. As a result, the demand for fault tolerance strategies is the main subject of many types of research targeting System-on-Chip (SoC) designs. In particular, retransmission mechanisms are one of the most used solutions in the Network-on-Chip (NoC) operation, but these mechanisms...
Many-core systems are increasingly popular in embedded systems due to their high-performance and flexibility to execute different workloads. These many-core systems provide a rich processing fabric but lack the flexibility to accelerate critical operations with dedicated hardware cores. Modern Field Programmable Gate-Arrays (FPGAs) evolved to more than reconfigurable devices, providing embedded hard-core...
This paper evaluates the efficiency and performance impact of a dual-core lockstep as a method for fault-tolerance running on top of FreeRTOS applications. The method was implemented on a dual-core ARM Cortez-A9 processor embedded into the Zynq-7000 APSoC. Fault injection experiments show that the method can mitigate up to 63% on the FreeRTOS applications. This result is very near to the mitigation...
Operating CMOS circuits at subthreshold supply voltages is an attractive solution for substantial energy reduction, at the expense of strong timing performance degradation, for a broad range of battery operated appliances. One of the challenges of this approach in current technology nodes is the reduced available noise margin when operating at low supplies. This paper evaluates the Static Noise Margin...
Support Vector Machines (SVMs) are supervised learning models of the machine learning field whose performance strongly depended on its hyperparameters. The Bio-inspired Optimization Tool for SVM (BIOTS) tool is based on a Multi-Objective Particle Swarm Algorithm (MOPSO) to tune hyperparameters of SVMs. In this work, BIOTS is proposed along with a custom hardware design generator (VHDL) that implements...
Asynchronous quasi-delay-insensitive (QDI) circuits are a promising solution for coping with aggressive process variations faced by modern technologies, as they can gracefully accommodate gate and wire delay variations. Furthermore, due to their inherent robustness, such circuits are also promising for deep voltage scaling applications, where delays are orders of magnitude larger. However, QDI design...
In this work1 we present the design of a fully integrated wideband high efficiency power amplifier for 5G applications. The amplifier consists of two single ended common source stages, with a class-J power stage in the 28nm CMOS FD-SOI technology. Post-layout simulation results show a broadband behavior of the amplifier over 12 GHz of bandwidth with a saturated power of 16.2 dBm and a peak power added...
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