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In this paper, a novel 10 bit 20 MS/s, low power, pipelined ADC using both capacitor and opamp sharing techniques is proposed. In the proposed ADC, feedback capacitors in the first four stages are shared between adjacent stages in order to decrease the power dissipation of the opamps used in these stages. The opamps in the six pipeline stages are also shared between adjacent stages in pairs for further...
Background: Domino logic is widely used in modern digital systems because of easy implementation with less number of transistors and high speed. The pre-charge and evaluation phases of the domino logic, leads to enormous transitions at the output. This switching of the output is undesirable as it leads to more dynamic power dissipation. Methods: This achieved by the using the structures such as True...
Managing the power consumption of circuits and systems is challenging not only during functional operations but also during manufacturing test. This paper discusses industrial practices in this area. It is organized into three main parts. First, we give necessary background and discuss issues arising from excessive power dissipation during test application. Then, we provide an overview of industrial...
This paper presents a power-efficient 100-MS/s, 10-bit asynchronous successive approximation register (SAR) ADC. It includes an on-chip reference buffer and the total power dissipation is 6.8 mW. To achieve high performance with high power-efficiency in the proposed ADC, bootstrapped switch, redundancy, set-and-down switching approach, dynamic comparator and dynamic logic techniques are employed....
The continuous growing demand of portable battery-powered electronics devices hunts for Nano-electronic circuit design for ultra-low power applications by reducing dynamic power, static power and short circuit power. In sequential circuit elements of an IC, a notable amount of power dissipation occurs due to the rapid switching of high frequency clock signals, which do not fetch any data bit or information...
Power dissipation during scan testing of modern high complexity designs could be many folds higher than the functional operation power, which is a well established observation. High test power dissipation can severely affect the chip yield and hence the final cost of the product. This makes it of utmost important to develop low power scan test methodologies. In this work we have proposed a modified...
In today's world power consumption is a burning issue. Research is going on to find out various new power efficient design techniques. Power dissipation could be reduced by transforming continuous-time current-steering circuits into discrete-time charge-steering circuits. Charge steering shows all potential to emerge as an effective technique to reduce power dissipation for high-speed circuits. This...
Today's major concerns in designing VLSI circuits have been the amount of power dissipated by these circuits. The Adiabatic logic technique is becoming an answer to the problem of power dissipation. The term ‘Adiabatic’ refers to the change of state that occurs without the loss or gain of heat. The adiabatic switching technique reduces the power dissipation during switching events. But, adiabatic...
In this paper, the design of sample and hold (S/H) circuit for 16 bit 100MS/s pipelined ADC is presented. A high performance and low power dissipation operational trans-conductance amplifier (OTA) is realized by optimizing circuit configuration and adopting switched-capacitor dynamic bias technology. A double gate-bootstrapping switch is used as the sample and hold switch to enhance the sampling linearity...
Finding input sequences that cause switching activity burst (power virus) and consequently peak power dissipation is an essential issue in design of sequential digital circuits. This paper presents a novel technique for computing the power virus inputs from the very first step of the synthesis flow where the finite state machine is typically described in the form of Signal Transition Graph (STG) and...
To draw an accurate relationship between power dissipation and speed is a challenging problem in operational Amplifier with switch capacitance. However, transformation of current steer circuit into charge steer is an efficient technique to reduce power dissipation even at higher speed. In this paper, an efficient model is proposed to estimate the 1st and 2nd stage operational Amplifier's power dissipation...
Low power design is gaining prominence due to the increasing need of battery operated portable devices with high computing capability. It is the critical issue in ASIC design, as featured size is scaled down. The reliability of integrated circuit depends on the heat dissipated in the circuit. A large fraction of the power consumed is due to the clock distribution network and the high switching activity...
This paper proposes a novel low-power burst-mode clock recovery circuit (CRC) based on analog phase interpolator (PI). Accordingly, we employed a new configuration for PI-based CRC in which a novel architecture is utilized for double-edge triggered sample-and-hold (DT-SH). In the proposed DT-SH one buffer is shared between two single-edge triggered SH (ST-SH) resulting in great reduction of total...
The need to design and develop high performance and high speed VLSI systems such as NOCs in networking or SOCs in communication and computing has shifted the focus from traditional performance parameters towards the analysis of power consumption. In such devices managing the power among the domains of a system is of real concern. Hence, the low power design techniques namely: clock gating, power gating,...
With the increase in the demand for high performance and high speed VLSI systems such as network processors in networking or SOCs in communication and computing has shifted the focus from traditional performance parameters towards the analysis of power consumption. The power budget and management among the domains of a system is of real concern. Hence, the power aware design using clock gating, power...
Power dissipation is one of the key parameters when designing digital circuits. While an ASIC can be exactly fitted to the requirements, targeting an FPGA means to select one of many commercially available FPGAs having different power characteristics.
Binary Machines (BMs) are a generalization of Linear Feedback Shift Registers (LFSRs) in which a current state is a nonlinear function of the previous state. It is known how to construct a BM generating a given completely specified binary sequence. In this paper, we present an algorithm which can efficiently handle the case of incompletely specified sequences. Our experimental results show that it...
Dual edge triggering is an effective method for reducing the power consumption in the clock distribution network. This paper compares two existing design of flip-flop CDMFF and CPSFF with the proposed design of the dual edge triggered flip-flop (DE-CPSFF). The design eliminates the redundant transitions of internal nodes when current data is same as the previous one using conditional technique. This...
Managing the power consumption of circuits and systems is challenging not only during functional operations but also during manufacturing test. In this paper, we first explain why it is important to control power consumption during test application. We will introduce the basic concepts and discuss issues arising from excessive power dissipation during test. Then, we explain how it is possible to control...
The System-On-Chip (SoC) revolution challenges both design and test engineers, especially in the area of power dissipation. Generally, a circuit or system consumes more power in test mode than in normal mode. This extra power consumption can give rise to severe hazards in circuit reliability or, in some cases, can provoke instant circuit damage. Moreover, it can create problems such as increased product...
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