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Recently, a passive device — memristor has received wide attention in nano-scale design due to its applications in the area of nanoelectronic memory design, neuromorphic computing and logic design. This passive element is non-volatile in nature and has dual properties of memory and resistor. In recent time, the application of this device in designing high speed logic circuits has now opened a new...
In this paper we present a smart handheld system for point of care biosensors. The system consists of a novel multi-path potentiostat module which performs electrochemical measurements on disposable test strip. The strip provides a port for applying bio-sample such as blood or urine. The analyte port on the disposable strip is designed with 3 sets of 3 electrodes (Working, Reference and Counter electrodes)...
The majority voter plays the core role in the Triple-modular redundancy (TMR) based fault tolerant scheme. This work targets to implement a novel fault tolerant structure of the majority voter for the implementation of TMR using Quantum-dot cellular automata (QCA), a viable alternative nanotechnology to current CMOS VLSI. The proposed fault-tolerant voter circuit itself can tolerate a fault and give...
In this paper we present a novel low power 6-bit Flash analog-to-digital converter design using charge steering amplifier for RF applications. The architecture and performance of the designed ADC is described in detail and compared with conventional and other Flash ADCs. The proposed design offers lower power consumption by using a charge-steering amplifier based comparator; the power supply voltage...
Hardware cryptographic circuits emerge in the field of cryptography as an alternative of software rendition where the analysis of the dissipated power causes the major attacks like DPA and SPA which are formally executed on the classical circuits. The paper proposes a novel design of cryptographic circuit based on the popular RSA algorithm using fast Modular Multiplier designed with reversible logic...
Latency, Area, and Power are three important metrics that a VLSI designer wants to optimize. However, often one of these may have to be optimized at the cost of another or the other two. Depending on the application scenario, choice of the metric to optimize is made. In this paper, we consider hardware implementations of a number of cryptographic primitives and present a number of optimizations. We...
This paper describes the CMOS implementation of variable output voltage, multiphase switched capacitor step-down DC-DC converter with a large number of target voltages using Sigma-Delta Feedback Control Loop. The number of target voltages generated using n-flying capacitors are of the order of 2n. Expressions for equivalent series resistance Req, conduction, switching power loss and efficiency are...
Chip Multiprocessor (CMP) and System-on-Chip (SoC) designs have a large number of modules with billions of transistors embedded on a single die. While they offer very high performance, they also increase the design complexity and pose many challenges with one of them being floor-planning and placement. Floor-planning process is affected by and in turn effects physical characteristics, wire length,...
The performance of a comparator is significantly affected by the time taken to determine the unequal bit location so as to decide greater than, less than and equal to condition. Consequently, the delay will increase with the number of bits of a comparator. The reduction in delay so as to improve performance can be achieved with the introduction of multilevel look-ahead circuit. In this work, a unique...
Presents the introductory welcome message from the conference proceedings. May include the conference officers' congratulations to all involved with the conference event and publication of the proceedings record.
In this paper we present a new hybrid FA design (mix of CMOS and pass transistor logic styles), which aims at achieving higher speed but keeping power dissipation low, and hence targeting low PDP. Our proposed FA and seven other existing FA designs are simulated in spice, using 45 nm low power model file, using standard test bed and test pattern (56 input transitions) [1, 2], and the simulation results...
The need for low-power SRAM results in many design challenges in deep submicron technology. In this paper, 6T, 7T and 8T SRAM cells designed in 65nm bulk CMOS technology in the subthreshold region have been compared on the basis of various Figures of Merit (FoMs). The 7T and 8T SRAM cells are able to work at 200mV with 8T exhibiting highest Read Static Noise Margin (RSNM), Hold Static Noise Margin...
Digital Signal Processing (DSP) algorithms use multiplication as a most frequent operation. Hence multipliers are said to be dominant role players in the performance matrix of DSP application. The Fixed Width Multiplier (FWM) architecture in DSP application, itself are power efficient, most of the related work is reported on error correction. This paper extends the work of one of the bests papers...
This paper proposes the design of an 8-bit segmented current steering (CS) digital to analog converter (DAC), which uses Chinese abacus technique to improve both static and dynamic performances. Chinese abacus DAC is simple, occupies less area and shows better linearity compared to binary DAC. In conventional segmented CS architecture, the MSB is implemented in unary and LSB is implemented in binary...
DC-DC power converters based on switched capacitor circuits are widely used to realize different power supply domains in SOC chips. They can be classified as Analog Mixed Signal circuits. Current approaches to their verification is primarily based on simulating their transistor level netlist in circuit simulators. In this paper an approach to formally verify them using simulation traces is proposed,...
The advancements in emerging interconnects for Networks-on-Chip (NoCs) brings with it promising solutions to integrate single-hop long-range high-bandwidth on-chip links to achieve enhanced network performance. The use of these lie in the design of modern heterogeneous systems with increasing number of processing blocks, which may include application specific unconventional topologies. In this work,...
High level synthesis tools are an attractive option for rapid prototyping and implementation of hardware designs. In this paper we present a case study of using such a tool for the design and implementation of an FFT core for use in a wireless modem. The optimizations used for directing the conversion of C code to hardware are discussed and the impact of the different directives is analyzed. The resulting...
This paper addresses estimation of decoupling capacitance (decap) at sub-module stage based on their power dissipation and proper allocation of decap at the pre-layout level. Decap being in between power and ground distribution networks acts as local charge storage and effectively reduces rapid transients in the supply drop. Therefore, present trends in VLSI design are inclined towards the placement...
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