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In this paper we present a novel scheme to perform firmware verification using a graphical Colored Petri Net (CPN). CPNs provide modeling features for concurrency, communication and synchronization as well as hierarchical abstraction and timing analysis. These features are used to perform firmware validation of the UEFI USB bus initialization. The CPN representation provides better visualization support...
Recent advancements in video processing make video-based heart rate (HR) estimation possible. Building on this burgeoning field, we adapted an existing video-based HR estimation method to produce more robust and accurate results. Specifically, we removed periodic signals from the recording environment by identifying (and removing) frequency clusters that are present the face region and background...
In an effort to create a full-color holovideo display, a wavelength-multiplexing LiNbO3 crystal is designed. Fabrication parameters are presented. Results of tests and measurements are presented, as well as the procedures used to obtain them. By matching the bandwidth of the LiNbO3 to that of current GPUs, the display is able to efficiently process large amounts of data.
Securing data in machine to machine scenario is of paramount importance. With the evolving of Internet of Things (IoT) market, data should be protected from eavesdropper. Of the available cryptographic algorithms, International Data Encryption Algorithm (IDEA) is one of the most secured and highly accepted algorithm to a broad range of applications. This paper presents implementation of IDEA cryptographic...
In this paper, we propose a speech enhancement method that works effectively in highly noisy environments. The proposed method emphasizes the speech signal buried in noise without noise estimation. A p-th power amplitude spectrum is inverse Fourier transformed with the phase information of the noisy speech signal. Experiments show that as the amount of noise is increased, the proposed method provides...
This paper presents a robust reference-less multilevel memristor based Resistive RAM (RRAM) module. In contrast to similar multilevel RRAMs, the proposed multilevel module eliminates the need for any comparing reference level. Because of the use of a differential 1T2M memory cell, data decoding is performed with traditional standard cells. On the other hand, no feedback loops are needed to ensure...
Recently, controlling the surrounding world by just the power of our thoughts has become a reality using Brain Computer/Machine Interface (BCI/BMI). Enabling handicap people to control artificial limbs is one of the most important goals of BCI. There are challenges in providing the usability of BCI implants because most of the BCI sensors are non-practical or increases the infection hazard to the...
A technique to prevent deconvolution object from ringing errors in Lucy-Richardson-deconvolution (LRDec) iteration cycles is proposed, which is required for inversely analyzing complex-shaped Random Telegraph Noise (RTN) effects on SRAM margin variations. The proposed feedback gain phase alignment successfully circumvents the unwanted errors and makes it possible to avoid the need to give up on a...
Hardware security is a major concern in the intellectual property (IP) centric integrated circuits (IC). 3-D IC design augments IP centric designs. However, 3-D ICs suffer from high temperatures in their middle tiers due to long heat dissipation paths. We anticipate that this problem would exacerbate the hardware security issues in 3-D ICs. Because, high temperature leads to undesired timing characteristics...
In this paper, a global algorithm for human action, facial and gesture recognition is presented. The proposed algorithm depends on the extraction of multiple transform domain features and Canonical Correlation Analysis (CCA) for features fusion and classification. The proposed algorithm achieved the best reported results for facial and facial expression recognition. Excellent comparable results were...
The paper presents a cascoded power stage with automatic dead time generation. The circuit is using the inter-transistor node voltages of the cascode configuration as feedback control signals to delay turning ON the power transistors. The circuit is designed as the output stage of a fully-integrated buck converter. The steady-state operation is described. The waveforms simulated on 45-nm CMOS process...
We consider a transmission line model connected to a nonlinear component at one boundary and a linear resistor at the other boundary. We show that when the nonlinearity at the boundary is hysteretic, chaotic behavior occurs, which propagates along the transmission line creating a complex pattern which is an example of severe signal distortion. In a real circuit, such signals, could be transmitted...
A digital calibration technique for folding-integration/cyclic cascaded (FICC) analog-to-digital converters (ADCs) is proposed in this paper. The calibration is done by compensating non-ideal errors in digital domain. The errors generated during each converting cycle and the final effects of them are calculated with properly established model in charge domain according to the behaviors of the FICC...
Smoothing filters are low pass filters commonly used to reduce the details levels in image processing. This work suggests the use of a special family of low pass filters, namely the linear-phase exponential filters to perform image smoothing. The linear-phase exponential filters are used because they can be recursively implemented, which results in significant hardware savings. This work's contribution...
Molybdenum disulfide (MoS2) is a new emerging 2D material like graphene for applications in solid state, optoelectronic and many other devices. MoS2 has good bandgap for electronic applications. Graphene has almost zero bandgap and that will lead to impractical switching operation for MOSFET. MoS2 based switching devices will not have this limitation. The 2D flat nature of MoS2 would be suitable for...
POWER8™ (P8) processor is a 12-core, 649mm2, 4.2B transistor chip fabricated in IBM's 22nm SOI technology with 2.5× socket performance improvement over its 32nm predecessor, POWER7+, driven by big data application and power efficient computing. Highly distributed chip voltage regulator achieves a peak power efficiency of 90.5%. Resonant clock design is used in 13 clock meshes to achieve about 4% power...
This paper proposes an MDLL/PLL dual-path clock generator. By splitting a single delay line into two halves, both a voltage controlled delay-line (VCDL) and a voltage controlled oscillator (VCO) can be implemented. Since both the integral and proportional paths can be configured in this way, stabilizing zero is inherently obtained. Elimination of the zero-insertion resistor in a loop-filter mitigates...
In this paper, we present a differential current-mode pulsed flip-flop (DCMPFF) for low-power clock distribution using a representative 45nm CMOS technology. Experimental results show that the DCMPFF has 47% faster clock-to-output (CLK-Q) delay than a traditional voltage-mode (VM) pulsed flip-flop. When the DCMPFF is integrated with a differential current-mode clock distribution, the differential...
This paper presents the current-voltage (I–V) characteristics of the recently proposed Silicon-on-Ferroelectric Insulator Field Effect Transistor (SOFFET). In this work we have concentrated on Partially Depleted (PD) structure. PD-SOFFET is based on the silicon-on-insulator (SOI) device technology and utilizes a negative capacitance that can be achieved by inserting a layer of ferroelectric insulator...
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