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Presents the introductory welcome message from the conference proceedings. May include the conference officers' congratulations to all involved with the conference event and publication of the proceedings record.
In this paper we present a smart handheld system for point of care biosensors. The system consists of a novel multi-path potentiostat module which performs electrochemical measurements on disposable test strip. The strip provides a port for applying bio-sample such as blood or urine. The analyte port on the disposable strip is designed with 3 sets of 3 electrodes (Working, Reference and Counter electrodes)...
The majority voter plays the core role in the Triple-modular redundancy (TMR) based fault tolerant scheme. This work targets to implement a novel fault tolerant structure of the majority voter for the implementation of TMR using Quantum-dot cellular automata (QCA), a viable alternative nanotechnology to current CMOS VLSI. The proposed fault-tolerant voter circuit itself can tolerate a fault and give...
In this paper we present a novel low power 6-bit Flash analog-to-digital converter design using charge steering amplifier for RF applications. The architecture and performance of the designed ADC is described in detail and compared with conventional and other Flash ADCs. The proposed design offers lower power consumption by using a charge-steering amplifier based comparator; the power supply voltage...
In this paper we present a new hybrid FA design (mix of CMOS and pass transistor logic styles), which aims at achieving higher speed but keeping power dissipation low, and hence targeting low PDP. Our proposed FA and seven other existing FA designs are simulated in spice, using 45 nm low power model file, using standard test bed and test pattern (56 input transitions) [1, 2], and the simulation results...
The need for low-power SRAM results in many design challenges in deep submicron technology. In this paper, 6T, 7T and 8T SRAM cells designed in 65nm bulk CMOS technology in the subthreshold region have been compared on the basis of various Figures of Merit (FoMs). The 7T and 8T SRAM cells are able to work at 200mV with 8T exhibiting highest Read Static Noise Margin (RSNM), Hold Static Noise Margin...
Digital Signal Processing (DSP) algorithms use multiplication as a most frequent operation. Hence multipliers are said to be dominant role players in the performance matrix of DSP application. The Fixed Width Multiplier (FWM) architecture in DSP application, itself are power efficient, most of the related work is reported on error correction. This paper extends the work of one of the bests papers...
This paper proposes the design of an 8-bit segmented current steering (CS) digital to analog converter (DAC), which uses Chinese abacus technique to improve both static and dynamic performances. Chinese abacus DAC is simple, occupies less area and shows better linearity compared to binary DAC. In conventional segmented CS architecture, the MSB is implemented in unary and LSB is implemented in binary...
DC-DC power converters based on switched capacitor circuits are widely used to realize different power supply domains in SOC chips. They can be classified as Analog Mixed Signal circuits. Current approaches to their verification is primarily based on simulating their transistor level netlist in circuit simulators. In this paper an approach to formally verify them using simulation traces is proposed,...
The advancements in emerging interconnects for Networks-on-Chip (NoCs) brings with it promising solutions to integrate single-hop long-range high-bandwidth on-chip links to achieve enhanced network performance. The use of these lie in the design of modern heterogeneous systems with increasing number of processing blocks, which may include application specific unconventional topologies. In this work,...
High level synthesis tools are an attractive option for rapid prototyping and implementation of hardware designs. In this paper we present a case study of using such a tool for the design and implementation of an FFT core for use in a wireless modem. The optimizations used for directing the conversion of C code to hardware are discussed and the impact of the different directives is analyzed. The resulting...
This paper presents a binary frequency shift keying (BFSK) demodulator for low intermediate frequency (IF) receivers and an FPGA based bit error rate (BER) measurement platform for the same. The custom made demodulator is fabricated in 180 nm CMOS mixed mode technology, which occupies an area of 0.09 mm2 and consumes 80 μW power from 1.8 V supply. When integrated with a low IF (2 MHz) receiver front...
A High CMRR, High-resolution signal processing bioASIC circuit for wireless and wearable systems is presented. The chip consists of High CMRR Instrumentation Amplifier (IA) integrated with high accuracy pipeline ADC. The bio-ASIC front-end is built using current balance IA circuit followed by high pass and low pass filters. A High resolution, wide dynamic range, integrated Pipeline ADC allows input...
Hardware Trojans can be inserted by an adversary at any phase of IC manufacturing. In this paper, a methodology is proposed to detect Trojans inserted after design sign-off i.e the Trojan insertion occurs at layout level. In such attack models, golden IC are not always available in all cases, thus requiring golden IC free detection methodologies. This work exploits the concept of symmetric path delays...
NoC has a significant impact on the power, area and performance of multi-core architectures. The contribution of NoC in the total power budget of a CMP is approximately 30 to 40% [1], and the input buffers of router consume most of it. Therefore, the designers need to design a low power communication architecture of NoC by reducing the power consumption of buffers. In the existing techniques, virtual...
Presents the introductory welcome message from the conference proceedings. May include the conference officers' congratulations to all involved with the conference event and publication of the proceedings record.
In this paper, we have analyzed the temperature dependent average IR-Drop and delay of side-contact multi-layer graphene nanoribbon (MLGNR) based power interconnects. The above analysis has been performed using our previously developed model using 16nm ITRS technology node. For a temperature ranges from 150K to 450K, the variation of resistance of MLGNR interconnect is ∼2–5× lesser than that of traditional...
Micro-Electro-Mechanical System (MEMS) sensors are integrated with suitable signal conditioning unit (SCU) to provide usable output. Though the output of the SCU can be either analog or digital, digital output is often required in many system applications where other components are mostly digital. This work integrates a sigma-delta (ΣΔ) Analog to Digital Converter (ADC) with an analog front-end for...
In this work we have proposed a fault tolerant reconfigurable Network-on-Chip (NoC) architecture that can endure router faults with graceful degradation in network performance. The routers which form the main building block of the interconnect network, have been modified to support multi-core connections. In case of router faults, the modified routers help to recover the healthy cores connected with...
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