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The generalization of Property Directed Reachability (PDR) for the theory QF_BV presented in [1] outperforms the original formulation if the required inductive invariant can be represented efficiently as a set of polytopes. However, many QF_BV model checking instances do not belong in this class and can be solved quickly with the original PDR algorithm. In this paper, we present a hybrid approach...
To enable the capacitance extraction of chip-scale large VLSI layout using the floating random walk (FRW) algorithm, two techniques are proposed. The first one is a virtual Gaussian surface sampling technique. It makes efficient random sampling on the Gaussian surface for complex nets with vias, and optimizes the sampling scheme to reduce the time of random walk. The other one is a parallelized, improved...
Neuromorphic engineering takes inspiration from biology to design brain-like systems that are extremely low-power, fault-tolerant, and capable of adaptation to complex environments. The design of these artificial nervous systems involves both the development of neuromorphic hardware devices and the development neuromorphic simulation tools. In this paper, we describe a simulation environment that...
A multi-chip custom digital super-computer called eBrain for simulating Bayesian Confidence Propagation Neural Network (BCPNN) model of the human brain has been proposed. It uses Hybrid Memory Cube (HMC), the 3D stacked DRAM memories for storing synaptic weights that are integrated with a custom designed logic chip that implements the BCPNN model. In 22nm node, eBrain executes BCPNN in real time with...
This work focuses on volume diagnosis for identifying systematic faults in lower-yield wafers, whose yields are lower than baseline level due to systematic faults during mass production. We develop a model-based volume diagnosis method. To diagnose accurately using the fail data with one lower-yield wafer, we apply modeling techniques for handling pseudo-faults and random faults in the fail data....
Recent advances in spintronics devices make it possible to open a new era of microelectronics. In this paper, we review the spintronics devices utilizing spin-transfer torques (STTs) and spin-orbit torques (SOTs) developed in recent years. The progresses of two-terminal STT device with CoFeB-MgO based magnetic tunnel junction (MTJ), three-terminal magnetic domain wall (DW) motion device with Co/Ni...
The recent research reveals that the bit error rate of a NAND flash cell is highly dependent on the stored data patterns. In this work, we propose Data Pattern Aware (DPA) error protection technique to extend the lifespan of NAND flash based storage systems (NFSS). DPA manipulates the ratio of 1's and 0's in the stored data to minimize occurrence of the data patterns which are susceptible to bit error...
This paper aims at presenting how new technologies can overcome classical implementation issues of Neural Networks. Resistive memories such as Phase Change Memories and Conductive-Bridge RAM can be used for obtaining low-area synapses thanks to programmable resistance also called Memristors. Similarly, the high capacitance of Through Silicon Vias can be used to greatly improve analog neurons and reduce...
Conventional CMOS integrated circuits suffer from serve power and scalability challenges as technology node scales into ultra-deep-micron technology nodes. Alternative approaches beyond charge-only based circuits. In particular, spin-based devices or integrated circuits show promising merits to overcome these issues by adding the spin freedom of electrons to the electronic circuits. Spintronics has...
With memory estate increasing in System-On-Chips and highly integrated products, memory defects and wearout effects are the determining factor in the chip's yield loss and reliability. In this paper, a multiple cache-based Built-in Self-Repair scheme is proposed that is able to repair from the word level down to the bit level. Moreover, it is proved that the level of segmentation does not affect the...
In order to increase the yield of 3-D IC, fault-tolerance technique to recover failed TSV is essential. In this paper, an architecture of TSV recovery by using scan-chain test TSV is proposed. With the architecture, only a small amount of redundant TSVs is required to be inserted. Extra TSV area that occurs by our method is much less than that of other methods. Moreover, a 3-D IC scan-chain optimization...
Multi-core machines enable the possibility of parallel computing in Automatic Test Pattern Generation (ATPG). With sufficient computing power, previously proposed parallel ATPG has reached near linear speedup. However, test inflation in parallel ATPG yet arises as a critical problem and limits its practicality. Therefore, we developed a parallel ATPG system that incorporates (1) concurrent interruption...
In this paper, we propose a run-time mapping algorithm, CASqA, for networked many-core systems. In this algorithm, the level of contiguousness of the allocated processors (α) can be adjusted in a fine-grained fashion. A strictly contiguous allocation (α = 0) decreases the latency and power dissipation of the network and improves the applications execution time. However, it limits the achievable throughput...
Resilient techniques are commonly employed for dynamic and static variation tolerance. In this paper, we present an adaptive clocking technique that achieves 31% throughput increase with 15% energy reduction, and an adaptive interconnect fabric technique that increases bandwidth by 63% with 14.6% energy reduction. We also discuss variations in many-core microprocessors and some techniques to enable...
Heterogeneous many-cores can deliver high performance or energy efficiency. There are two orthogonal ways to improve performance: 1) scale-out by exploiting thread-level parallelism, and 2) scale-up by enabling core heterogeneity. Predicting the performance of such architecture is increasingly challenging. We propose a comprehensive performance model Amphisbaena, or Φ, built from two orthogonal functions...
Microprocessors fabricated at nanoscale nodes are exposed to accelerated transistor aging due to Bias Temperature Instability and Hot Carrier Injection. As a result, device delays increase over time reducing the Mean Time To Failure (MTTF) of the processor. To address this challenge, many (micro)-architectural techniques target the execution stage of the instruction pipeline, as this one is typically...
In this work, we propose a new, accurate, and comprehensive analytical model for Network-on-Chip (NoC) performance analysis. Given the application communication graph, the NoC architecture, and the routing algorithm, the proposed framework analyzes the links dependency and then determines the ordering of queuing analysis for performance modeling. The channel waiting times in the links are estimated...
The number of control pins used is a major factor affecting the manufacturing cost of Digital Microfluidic Biochip (DMFB). Pin-count on a DMFB can be reduced by sharing of control pins between electrodes. Most existing works on reducing pin-count are problem specific. Problem specific optimizations result in DMFB that can only perform certain specific bioassays. Cross-Referencing DMFB has a full array...
We present ABCD-NL, a technique that approximates non-linear analog circuits using purely Boolean models, to high accuracy. Given an analog/mixed-signal (AMS) system (e.g., a SPICE netlist), ABCD-NL produces a Boolean circuit representation (e.g., an And Inverter Graph, Finite State Machine, or Binary Decision Diagram) that captures the I/O behaviour of the given system, to near SPICE-level accuracy,...
Reconfigurable radio frequency (RF) system is an emerging component to mitigate the growing engineering cost for wireless chip design. In this paper, we propose a new methodology for efficient programming of reconfigurable RF receiver. The proposed method is facilitated by two novel techniques: two-phase relaxation search and Pareto-based search space reduction. Our numerical experiments demonstrate...
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