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A new topology of a low-power F-band reflection amplifier for active reflectarrays is proposed and demonstrated using a CMOS fully depleted silicon-on-insulator 28-nm process. The design enables frequency response and center frequency tuning, as well as phase control of the reflected signal. The chip consumes a core area of only $90\times 80~\mu\text{m}^{2}$ and is incorporated into a $2\times 2$ ...
This research paper introduces a fully controllable negative inductor and two R-L Immittance simulator using Differential Voltage Current Conveyor (DVCC) and some passive components. One of the immittance simulators is a parallel RL and other is series R and L. All the three simulators use two resistors and one capacitor. Workability of all the simulators are tested by 0.5μm CMOS Technology.
The immense work presented in this paper is a high frequency sinusoidal oscillator using positive second generation current controlled conveyor (CCCII+) with minimum passive components. CCCII is implemented using single Current Feedback Operational Amplifier (CFOA) and single Operational Trans-conductance Amplifier (OTA). The frequency (time period) of CCCII is tuned to a maximum of 4 MHz using external...
Mosquito-borne diseases, such as malaria and dengue, are major health concerns in the Philippines. This research provides a CMOS RC oscillator that operates at frequency based on the wing-beat frequency of male mosquitoes and dragonflies, in order to produce ultrasonic signal that repels biting female mosquitoes. This work presents the design and chip layout of CMOS RC oscillator which comprised of...
In this paper, a novel analytical model for current-mode-logic D flip-flop (CML-DFF) frequency divider is presented. With the help of this model, a tunable inductor-less divide-by-2 CML-DFF divider operating from 0.8–30 GHz with digital frequency calibration is designed and simulated in TSMC 90 nm CMOS process. The proposed divider has a tunable frequency locking range of 190% at peak-to-peak injection...
In this paper, a new realization of a fully-differential (F-D) first-order all-pass filter (APF) operating in current mode (CM) is presented. In the proposed F-D CM APF a single adjustable current amplifier (ACA) and two current followers (CFs) with non-unity gain are used as active building blocks. Considering the input intrinsic resistance of CFs as useful active filter parameter, the proposed filter...
This paper presents an ultra-low-power low-voltage Class-AB Fully Differential Operational Amplifier designed in 45-nm CMOS technology. The proposed circuit uses transistors operating in sub-threshold region for low-power and low-voltage operation. The proposed Op Amp offers an open-loop gain of 74.6 dB, 1 MHz unity gain frequency, 50-degrees Phase Margin, and 91.55 dB common-mode rejection ratio...
This paper presents a high-voltage output stage producing signals well beyond the voltage ratings of standard devices in a nanometer-scale CMOS technology. The driver is a two-level, switched capacitor output stage that combines both voltage conversion and pulse drive. The design is highly modular and enables extended device-stacking seamlessly and with little overhead. The driver achieves a peak...
In this paper, a new realization of a first-order voltage-mode (VM) All-Pass Filter (APF) using a grounded capacitor, three resistors, and a single Current Follower (CF) with non-unity gain is presented. The number of external resistors in the proposed VM APF can be reduced to two by considering the input intrinsic resistance of the CF as a useful active parameter. In comparison to the second-generation...
In this paper, an approach towards high speed current mode based SAR ADCs is presented. The main focus is placed on the design of a unary single-sided current steering DAC working with a binary search algorithm inside the SAR loop. Reflecting the fact that current source matching and precise current settling are the most important static and dynamic properties of the current steering DAC in a current...
The resistive switching behavior recently observed in silicon oxide (SiOX) makes this material attractive to embedded resistive random access memory (RRAM) fabrication due to process compatibility. In SiOX-based RRAM devices, switching mechanism is closely correlated with defects in the oxides. Therefore developing a method to control the defects is necessary for performance enhancement. In this paper,...
This paper presents a high-voltage driver in nanometer-scale, low-voltage SOI CMOS technology well beyond the voltage limits of standard devices. The drive level is near the voltage-tolerance limit of the body insulator. A novel, bidirectional, switched-capacitor output stage that combines both voltage-conversion and pulse-drive is introduced. The two-level driver is implemented in 45-nm SOI CMOS...
This paper presents a 12.8GS/s 32-way hierarchically time-interleaved SAR ADC with 4.6-bit ENOB in 65nm CMOS. The prototype utilizes multi-stage sampling and a cascode sampler circuit to enable greater than 25GHz 3dB effective resolution bandwidth (ERBW). We further employ a pseudo-differential SAR ADC to save power and area. The core circuit occupies only 0.23 mm2 and consumes a total of 162mW from...
A 4.5-GHz low-noise amplifier (LNA) utilizing a current-reused technique and a simple LC matching network is proposed. The implemented LNA presents a maximum gain of 35.22-dB by using inductive peaking technique, and a good input matching of 50Ω in the required band. An excellent noise figure (NF) of 2.255-dB was obtained in the frequency range of 4.5-GHz with a power dissipation of 5.04mW under a...
This paper presents a low power and high gain limiting amplifier for Gbps wireless communication system in 0.18μm CMOS technology. It incorporates negative active inductor, negative resistance and negative capacitance to boost gain and bandwidth. Drawing 2.8mA from 1.8V supply, the limiting amplifier achieves 1.25Gbps data rate and 52dB differential gain. The chip is fully integrated, which occupies...
This paper presents the design methods that allow to drastically limit an area of a recording channel in multichannel integrated circuits dedicated to neurobiology experiments. The techniques that are presented in this paper allow to apply them in a 3D pixel multichannel integrated systems where area limitations are very strict. Furthermore, these allow one to minimize main problems e\ xisting in...
The non-ideal behaviour of a classical comparator-based first-order relaxation oscillator is analysed. The influences of the comparator slew-rate and output resistance as well as the parasitic resistances of the reactive element are considered. Numerical simulations at system level and transistor level are given.
This paper presents a design and measurements of multichannel integrated circuits dedicated to recording of neurobiological signals. 64 recording channels have been implemented in a single chip using a commercially available CMOS 180 nm process. A single recording amplifier consumes only 25 µW from 1.8 V supply and occupies 0.13 mm2 of the silicon area. Its main parameters such as the low/high cut...
A 1.8-V 250-mA CMOS low-dropout regulator (LDO) with a current-efficiency rail-to-rail buffer to enhance load regulation is presented. The proposed buffer provides a push-pull output stage for driving pass device and pushes the parasitic pole far beyond the unity-gain frequency to improve phase margin of the LDO loop response. The proposed LDO has been implemented in a 0.35-μm CMOS process technology...
In this paper, a new compact realization of sinusoidal oscillator using modified current backward transcon-ductance amplifier (MCBTA) is reported. The proposed circuit employs a single MCBTA and four passive components including two grounded capacitors. The circuit provides completely de-coupled condition of oscillation (CO) of the frequency of oscillation (FO), i.e. no term in the CO is present in...
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