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Electrically active defects in silicon-based epitaxial layers on silicon substrates have been studied by Deep-Level Transient Spectroscopy (DLTS). Several aspects have been investigated, like, the impact of the pre-epi cleaning conditions and the effect of a post-deposition anneal on the deep-level properties. It is shown that the pre-cleaning thermal budget has a strong influence on the defects at...
The characterization of low-frequency (LF) noise is carried out in p-type Si passivated Ge FinFETs, comparing the performance of narrow (Wfin = 20 nm) and planar-like (Wfin = 100 nm) devices. The low-frequency noise is shown to be dominated by flicker noise, i.e., (1/fγ) where γ∼1, in the evaluated frequency range for both fin widths, which is governed by number fluctuations. Furthermore, narrow devices...
In this work, a comparative study between vertical silicon GAA TFETs and silicon GAA MOSFETs was realized, focusing on relevant analog parameters, as transistor efficiency, Early voltage, intrinsic voltage gain, unity gain frequency, and the product of the transistor efficiency multiplied by the unity gain frequency. The key parameter of comparison is the inversion coefficient (IC). The analysis was...
In this work the intrinsic voltage gain (AV) is for the first time experimentally analyzed for a planar Line-TFETs and its performance is compared with different MOSFET and point TFET architectures (FinFET and GAA:Gate-All-Around) at both room and high temperatures. The Line-TFET shows a much better intrinsic voltage gain than all studied MOSFET devices (FinFET and GAA). However, when it is compared...
In this work, the influence of the Ge amount at source on transistor efficiency and intrinsic voltage gain of vertical gate all around TFET is experimentally evaluated, comparing three different source compositions. The reference transistor has a source of 100% of Si, and the studied devices have 27% and 100% of Ge at the source. The increase of the Ge amount at source enhances the tunneling current,...
Germanium pFinFETs are evaluated from the viewpoint of effective hole mobility and low frequency noise performance. These parameters are measured for different fin widths and backside substrate bias in order to get a better insight in the underlying scattering mechanisms. For narrow devices, it was found that the peak effective mobility and the Coulomb scattering coefficient are limited due to the...
Hot carrier (HC) reliability is investigated at ‘on’ and ‘off’ state stress conditions in junctionless (JL) gate-all-around HK/MG nanowires. We discuss the reason of improved HC reliability in JL nanowire compared to the inversion-mode (IM) nanowire at ‘on’ state stress condition. Then we present the impact of ‘off’ state stress in the JL nanowire, considering that a high gate oxide field is applied...
This work presents an experimental analysis of the transconductance in vertical Ge source gate-all-around Tunnel-FETs for temperatures ranging from 100K to 400K. It was observed that the gm hump is related to the different conduction mechanisms which can be explained by the different temperature impact for each mechanism. This effect was also studied using numerical simulations.
This paper presents for the first time an experimental analysis of germanium pMOSFETs operating in conventional, dynamic threshold voltage (DT, where VBS = VGS) and enhanced dynamic threshold voltage (eDT, where VBS=k*VGS) modes. In addition, there are two different HfO2/Al2O3 gate stack thicknesses under evaluation. The subthreshold swing (SS) improves 60% in eDT (k = 2) mode compared to the conventional...
This paper studies the transport parameters of n-type FinFETs extracted using the Y-Function methodology, by comparing their dependence on the fin width and the crystallographic orientation for standard and rotated substrates as well as the influence of biaxial strain. The Y-Function has been applied with a recursive algorithm to improve its accuracy. The results obtained show that the low-field mobility...
Low frequency noise diagnostics is a powerful tool to study the quality of gate stacks and the different interfaces and also gives detailed information on the device performance and reliability. The influence of new materials, different processing treatments and alternative device concepts on the low frequency noise performance will be reviewed for a variety of advanced device technologies including...
We report a comprehensive evaluation of different device architectures from a device and circuit performance viewpoint: gate-all-around (GAA) nanowire (NW) FETs vs. triple-gate finFETs, both built using various doping schemes. GAA devices are obtained via a fins release process, high density compatible, at replacement metal gate (RMG) module, and outperform others per footprint. Junctionless (JL)...
This paper reviews the application of low-frequency noise and Random Telegraph Signal (RTS) studies on advanced memory devices, namely, Metal-Insulator-Metal capacitors with SrTiOx as insulator, peripheral transistors for Dynamic Random Access Memories and Resistive Random Access Memory structures. In the first two cases, flicker noise is used to analyze the quality or defectiveness of the gate stack,...
The effect of the S/D extensions architecture on the low-frequency noise and DC characteristics of Ultra-Thin Buried Oxide (UTBOX) SOI MOSFETs measured at zero/accumulated back-gate voltage is discussed. The undoped underlapped extensions were found to be responsible for an increased 1/f noise level and resistance of devices with extensionless architecture. The noise spectra of these devices also...
The low frequency noise measurements as a function of temperature are used as a non-destructive device characterization tool in order to evaluate the quality of the silicon film and to identify traps induced during the device processing in standard <100> and rotated <110> UTBOX n-type transistors. By comparing two methods, one to estimate the volume trap density and another to estimate...
Cu based metal trench is essential for the downscaling of interconnects for 20–10nm technologies, where it is important to optimize the materials and processing on the barrier and cap layer for a promising resistivity and electromigration (EM) performance. In order to shorten the period of process evaluation, a fast wafer-level EM characterization method is highly demanded rather than the conventional...
The impact of inelastic tunneling on the interpretation of flicker noise spectra and Bias Temperature Instability relaxation will be discussed in terms of a simple man's model. The impact of various parameters, like the barrier for capture or the relative position of the Fermi level with respect to the trap level is investigated for the Si/SiO2 system. Overall, it is derived that the extracted trap...
The low-frequency (LF) Noise of Ge planar pMOSFETs passivated with GeOx interfacial layer, followed by a post-Al2O3-deposition plasma treatment and fabricated in Ge-on-Si substrates, was analysed in this study. While interface state density values comparable with mid-gap Si/SiO2 can be achieved it is also important to study the density of border traps in the gate stack by LF noise. It is shown that...
The evolution of the 1/f noise and the resistance of extensionless Ultra-Thin BOX SOI nMOSFETs with decreasing gate length in comparison with standard ones is analyzed. It is revealed that the non-overlapped under-spacer regions define the resistance and 1/f noise behavior of extensionless devices.
The oxide trap density profile in DRAM peripheral nMOSFETs with Mg cap and different thermal budgets for in-diffusion of the metal ions has been investigated by low-frequency noise. It is shown that close to the SiO2/HfO2 interface a peak in the trap density is found, which disappears under a high thermal budget. No impact of Mg on the bulk oxide trap density in the HfO2 is observed.
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