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The Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) is a three days meeting bringing together the experts from Industry and Academia in technology, physics, modeling, simulation, and characterization of advanced nano-scale semiconductor-on-insulator and silicon-compatible devices from Europe and all over the world. For more than ten...
Mechanical stress has the potential to be an efficient performance booster for diverse emerging research devices based on tunneling phenomena, such as tunnel FETs, resonant tunnel FETs and reconfigurable FETs. The effect is highly dependent on the constellation between the stress source and the crystal orientation. Although stress engineering is well established for enhancement carrier mobility, it...
The optimization of Reconfigurable FET (RFET) devices is carried out in planar SOI technology. The electrostatic behavior, drive current and logic inverter operation are then discussed and compared with planar 28nm FDSOI devices.
We present semi-classical simulations of Gate-overlapped-Source Tunnel Field Effect Transistors (GoS-TFETs) taking into account the effects of trap-assisted tunneling, channel quantization, surface roughness, and density-of-state tails.
In this work the intrinsic voltage gain (AV) is for the first time experimentally analyzed for a planar Line-TFETs and its performance is compared with different MOSFET and point TFET architectures (FinFET and GAA:Gate-All-Around) at both room and high temperatures. The Line-TFET shows a much better intrinsic voltage gain than all studied MOSFET devices (FinFET and GAA). However, when it is compared...
A simulation study exploring the possibility of performance improvements related with the application of stress to nanowire TFETs is carried out. It is demonstrated that appropriate strain conditions, i.e., biaxial tensile strain, induce a remarkable enhancement of the on-state current thanks to bandgap reduction. However, a careful optimization of the device cross-section and strain level must be...
In conventional planar EHBTFETs, the interband tunneling phenomena responsible for the drive current takes place vertically in the section of the channel where top and bottom gates overlap. As a result, the horizontal extent of this overlapping between gates is the limiting factor for both the available band-to-band tunneling area and the occupied wafer space. Hence, any design seeking to increase...
In this paper we present a systematic study of GeSn n-FETs. First, process modules such as high-k metal gate stacks and NiGeSn - metallic contacts for use as source/drain contacts are characterized and discussed. GeSn alloys of different Sn content allow the study of the capacitance-voltage (CV) and contact characteristics of both direct and indirect bandgap semiconductors. We then present GeSn n-FET...
Thin-film transistors (TFTs) have been fabricated using atomic layer deposition (ALD) Nb-doped ZnO (Nb:ZnO) for the active layer. The optical and electrical properties of the Nb:ZnO TFTs for Nb cycle percentage between 0 and 12.5 % were studied. The optical band gap is seen to increase with Nb content, where a cycle percentage of 12.5% gives an increase of 0.27 eV to 3.54 eV. The device with 3.8%...
Single electron transistors (SET) featuring metal (Ni) electrodes and silicon nitride dielectric barriers prepared by atomic layer deposition are fabricated and tested. Electrical characterization of the devices reveals electrostatic energy parameters consistent with the parameters of the designed tunnel junctions. In addition, an analysis of temperature dependence of conductance confirms the formation...
High-k gate dielectric integration had been one of the key technological boosters for 45 nm CMOS technology and beyond. Just a couple technology nodes after adopting the hafnium-based high-k materials, the high-k scaling have already lost its momentum. It is anticipated that the EOT scaling will be in the rate less than 0.03 nm reduction/generation in coming technology nodes. Putting aside the fabrication...
Random Telegraph Noise (RTN) has been studied in ultrathin SOI MOSFET by introducing a new protocol which aims to identify unequivocally the single-trap RTN signals in optimum bias conditions for its electrical characterization. The methodology combines a modified Weighted Time Lag Plot algorithm assisted with 1/ƒ spectral scanning by gate bias. The procedure has been applied to study the influence...
The AlGaN/GaN omega-shaped nanowire FETs with different nanowire widths (W) have been fabricated. The effects of varying W on the performance of AlGaN/GaN omega-shaped nanowire FETs were investigated using low frequency noise (LFN) measurement. It was found that the noise characteristics of the device with narrow W show improved noise performances due to the accumulation of electrons in the volume...
We present simulations by the 2D drift-diffusion model of a quarter-micron NMOSFET at THz frequencies. The derivative of the current densities with respect to time is included in the model, which enables simulations of plasma oscillations. In contrast to the usual 1D transmission line models this approach includes all 2D effects of the device (parasitics, inhomogeneous channel, etc.). In the case...
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