The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
We have demonstrated photonic packaging compatible with standard, high-throughput, microelectronics assembly lines. We show a 1.3dB fiber-to-chip loss and 1.1dB chip-to-chip loss. We discuss the rationale behind this approach and compare to other packaging directions.
Self-aligned flip-chip assembly with sub-micron accuracy is of particular importance to low-cost manufacturing of single-mode opto-electronic components. The concept of alignment via surface tension force of melted solder has been proposed over two decades ago and appears simple. Yet, its effective working into manufacturing requires solving a few fundamental issues. In prior work, we introduced the...
Silicon photonics leverages microelectronic fabrication facilities to achieve photonic circuits of unprecedented complexity and cost efficiency. This efficiency does not yet translate to optical packaging, however, which has not evolved substantially from legacy devices. To reach the potential of silicon photonics, we argue that disruptive advances in the packaging cost, scalability in the optical...
This paper reports on the integration and packaging of embedded radial micro-channels for 3D chip cooling. A thermal demonstration vehicle (TDV) has been designed, fabricated and assembled. Radial micro-channels based on deep Si etching was integrated with a manifold chip to form a 2-layer chip stack, which has been assembled using a ceramic substrate and a Cu manifold. A test vehicle with an effective...
Flip-chip assembly with self-alignment down to sub-micron accuracy opens the door for low-cost assembly of micro-photonic chips. The surface tension of melted solder can be used to bring chips into alignment. The use of lithographically defined mechanical structures to stop the solder induced movement provides sub-micron alignment accuracy. However, several factors can impact the solder re-alignment...
Enabling single-mode photonic packaging in high-throughput microelectronic equipment can dramatically improve cost and scalability. We experimentally demonstrate such solution using 12-fiber interfaces and flipped-chip lasers. We measure −1.3dB peak fiber-to-chip transmission.
We demonstrate silicon photonic packaging that can be fully exercised in existing microelectronic packaging facilities. We show low optical loss and point towards notably improved assembly cost and scalability in both volume and optical port-count.
This paper presents a three-dimensional (3D) fully integrated high-speed multiphase voltage regulator. A complete switched-inductor regulator is integrated with a four-plane NoC in a two-high chip stack combining integrated magnetics, through-silicon vias (TSVs), and 45-nm SOI CMOS devices. Quasi-V2 hysteretic control is implemented over eight injection-locked fixed-frequency phases to achieve fast...
This paper presents a three-dimensional (3D) fully integrated high-speed multiphase voltage regulator. A complete switched-inductor regulator is integrated with a four-plane NoC in a two-high chip stack combining integrated magnetics, through-silicon vias (TSVs), and 45-nm SOI CMOS devices. Quasi-V2 hysteretic control is implemented over eight injection-locked fixed-frequency phases to achieve fast...
We demonstrate experimentally a flip-chip assembly with submicron three-dimensional alignment accuracy. We employ solder surface tension to push the flipped chip into lithographically defined alignment stops. During reflow, surface tension forces of the melted solder can move a chip by more than a hundred microns. We use these motions to obtain self-alignment by constraining the motions to lithographically...
In this paper, we will describe a new low cost solder bumping technology for use on wafers. The wafer IMS (injection molded solder) process can form fine pitch solder bumps on wafers, while offering greater solder alloy flexibility. This method is also applicable to form uniform solder bump heights when a wafer has different size and shape of I/O pads. The wafer IMS bumping process uses a solder injection...
In this paper, a novel assembly and packaging approach is proposed for 3D/2.5D chip stacks based on bumped substrates. The thinned chips are stacked using thermal compression bonding with “flat” metallization to reduce assembly complexity associated with conventional controlled-collapse-chip-connection (C4) solder bumps. Meanwhile, the laminate substrates are bumped with C4s using injected molten...
In this work, differential heating/cooling chip join process was developed for coreless flip chip packaging to minimize warpage change of coreless substrates during the bonding process. A chip was vacuumed to a bonder head and a coreless substrate was vacuumed on a base plate and they were held at different elevated temperatures during the bonding process. The temperature difference provides a substantially...
Wafer level underfill (WLUF), coated and B-staged on the wafer before dicing and flip chip bonding, protects and preserves interconnects and Back-End-of-Line (BEOL) structures by the presence of the underfill during the chip joining process. However, there are significant new challenges in formulating WLUF materials and developing the processes for area array flip chip packaging of silicon chips on...
A differential heating/cooling chip join method was developed for Pb-free flip chip packaging of ultra low-k (ULK) technology Si chips on organic substrates to prevent Chip-Package Interaction (CPI) — related damage upon chip joining. A chip was mounted to a bonder head and a substrate was located on a base plate and they were held at different elevated temperatures during the bonding process. The...
A new wafer level underfill material with filler content of 60 weight % was developed for high performance flip chip applications with lead free solder bumps. Systematic optimization of the viscosity behavior led to good spin coat ability even for the material with high filler loading. The material can be applied onto the bumped wafer with high uniformity up to a thickness of 100 |xm by spin coating...
We developed a latent curing, low outgassing wafer level underfill (WLUF) material and applied fast temperature ramping to achieve 100% electrically and metallurgically good flip chip solder joints. Also, void formation within the underfill material during the bonding process was minimized. Subsequently, these voids were virtually eliminated during a post cure process of the WLUF material which uses...
Injection molded soldering (IMS) technology has been developed for solder bumping of fine-pitch organic substrates. Pure molten solder is injected through a flexible film mask that is aligned to the recessed pad openings to form solder bumps on the substrate. The new substrate bumping method is a simple one pass operation for various size pads, with the capability of forming high solder volume on...
We report here preliminary results on a new Cu-cored flip chip structure combining C4NP (Controlled Collapse Chip Connect New Process) with Cu spheres for high density interconnections. C4NP is a new wafer bumping technology developed by IBM in which molten solder is injected into a mold and then transferred to the UBM (Under Bump Metallurgy) pads on the wafer. This simple and parallel process has...
We have studied the effect of thickness of Cu under bump metallization (UBM) from 5 mum, 10 mum to 50 mum on electromigration induced failure mechanism in flip chip solder joints. In the case of 5 mum Cu UBM, due to the direct current crowding effect at the UBM/solder interface, the failure mode induced by electromigration was the loss of UBM and the interfacial void formation at the cathode contact...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.