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Recently, a new right, the “Right to be forgotten”, has been defined for privacy protection. One approach to protect personal information is to control the data's lifetime or expiration. Here, a privacy-protection solid-state storage (PP-SSS) system is proposed, in which personal data is automatically invalidated within the hardware itself. In the proposed data-lifetime management (DLM) scheme, the...
A 3.3 × 3.2mm2 SoC in 0.35μm 2P/4M CMOS combines neurochemical sensing, on-the-fly chemometrics, and feedback-controlled stimulation to realize a “neurochemical thermostat” by differentiating electrically evoked brain dopamine levels from interferents in complex signals recorded in vivo and maintaining the levels between two user-set thresholds via closed-loop neuromodulation. The SoC features duty...
A new thermal tuning circuit for optical ring modulators enables demonstration of an optical chip-to-chip link for the first time with monolithically integrated photonic devices in a commercial 45nm SOI process, without any process changes. The tuning circuit uses independent 1/0 level-tracking and 1/0 bit counting to remain resilient against laser self-heating transients caused by non-DC-balanced...
A 12b 70MS/s sub-2 radix SAR ADC designed on Intel's 14nm tri-gate CMOS process is presented. It utilizes a startup calibration for correcting capacitor mismatches in its CDAC. The calibration is fully digital and doesn't require accurate references or input signals. The sub-2 radix architecture provides redundancy that improves speed. The comparator has a novel preamplifier that helps achieve low-noise...
An energy efficient descriptor generation (DG) processor is proposed for low-power object recognition (OR) processor, it has 3 low-power schemes: descriptor reuse (DR) algorithm, hierarchical pipeline (HP) architecture, and look-up table (LUT)-based nonlinear operation circuits. The DR OR algorithm reuses 58% descriptors from the previous frame. The HP employs upper 3-stage keypoint-level pipeline...
This paper proposes 3D stacked module consisting of image sensor and digital logic dies connected through inductive coupling channels. Evaluation of a prototype module revealed radiation noise from the inductive coils to the image sensor is less than 0.4-LSB range along with ADC code, i.e., negligible. Aiming at high frame rate image sensor/processing module exploiting this attractive off-die interface,...
A low-density parity-check (LDPC)-coded multiple-input multiple-output (MIMO) systems with iterative detection and decoding (IDD) chip is integrated in 1.33mm2 in 40nm CMOS. The maximum gross throughput is 794Mb/s for a 4×4 16-QAM configuration at 288MHz. The chip dissipates 135mW at 0.9V, achieving an energy efficiency of 170pJ/bit. Compared to non-IDD receivers, composed of state-of-the art MIMO...
The further growth of billions of wirelessly connected devices requires a technology infrastructure that can handle a massive increase in storage, computing power and bandwidth, some of it available via cloud computing, to enable number crunching at very large scale and at high volume, low cost and low power. The IoT applications or ‘smart devices’ require the following technology enablers: ultra-low...
Internet of Things regroups numerous applications. Among those, a common critical point is definitely power, as well as energy efficiency. 28nm UTBB FDSOI (28FDSOI) has demonstrated its superiority in terms of energy efficiency through numerous publications. This paper demonstrates the extra mile 28FDSOI is able to offer to designers, enabling on one hand ultra-low power (ULP) system-on-chips for...
A non-volatile programmable logic (NPL) with atom switch significantly accelerates performance of micro-controller unit. A low-power 32bit-CPU using a 65 nm-node Silicon-on-Thin-Box (SOTB) CMOS performs 1.95 DMIPS/MHz and 33 μW/MHz on 25 MHz and VDD=0.4V. When a software process in the CPU is offloaded to NPL, the 9 times faster processing speed and 3 times higher energy efficiency are realized. A...
This work introduces the first high-volume manufacturable metal-fuse technology in a 22nm tri-gate high-k metal-gate CMOS process. A high-density array featuring a 16.4μm2 1T1R bit cell is presented that delivers a record low program voltage of 1.6V. This low-voltage operability allows the array to be coupled with logic-voltage power delivery circuits. A charge pump voltage doubler operating on a...
A nonvolatile FPGA (NVFPGA) test chip, where 3000 6-input lookup table (LUT) circuits are embedded, is fabricated under 90nm CMOS/75nm perpendicular magnetic tunnel junction (p-MTJ) technologies. The use of a p-MTJ device makes data-backup-limitation free, which essentially eliminates damage control to nonvolatile storage devices. The use of a p-MTJ device also enables the extension towards dynamically...
This study proposes a 7T1R nonvolatile SRAM (nvSRAM) to 1) reduce store energy by using a single NVM device, 2) suppress DC-short current during restore operations through the use of a pulsed-overwrite (POW) scheme, and 3) achieves high restore yield by using a differentially supplied initialization (DSI) scheme. This initialization-and-overwrite (IOW) 7T1R nvSRAM improves breakeven-time (BET) by...
Enabling a high-density ReRAM product requires: developing a cell that meets a stringent bit error rate, BER, at low program current, integrating the cell without material damage, and providing a high-drive selector at scaled nodes. We discuss ReRAM performance under these constraints and present a 16Gb, 27nm ReRAM capable of 105 cycles with BER < 7×10−5.
A 13-ENOB, 5 MHz BW, 3.16 mW 3-bit continuous-time ΔΣ ADC sampling at 432 MHz is presented. For power efficiency, this design utilizes a hybrid feedback feed-forward loop topology with SAR quantizer, feed-forward compensated amplifiers, and push-pull DACs. Further power efficiency is gained by performing excess-loop-delay compensation (ELDC) using the SAR quantizer SC-DAC, which reduces power overhead...
A CMOS integrated 4-channel capacitive harmonic rejection baseband receiver and 4×4 MIMO analog core spatial filter demonstrate >65dB harmonic folding rejection over 48MHz, and >48.5dB signal separation across 3MHz baseband. The 65nm CMOS IC occupies 3.27mm2 active area and consumes 0.67mW–1.28mW.
A 410-GHz imager consisting of a 4th sub-harmonic mixer formed with an anti-parallel diode-connected NMOS transistor pair, and an on-chip antenna with 4.4-dB simulated gain is demonstrated in 65-nm CMOS. At −1.6-dBm power delivered to the LO input bond pad, the imager achieves 16.8-dB voltage conversion loss and 34.1-dB DSB noise figure. When the noise bandwidth is 1 kHz, sensitivity is −110 dBm,...
We demonstrate scaled High-Ge-Content (HGC) SiGe-OI finFET with Ge up to 71%, using a CMOS-compatible approach. For the first time, aggressively scaled HGC relatively-tall fins with vertical sidewalls and sub-10nm widths have been demonstrated using an enhanced 3D-Ge-condensation technique. An improved Si-cap-free HK/MG process featuring optimized IL has been developed resulting in scaled EOT and...
A leading edge 14 nm SoC platform technology based upon the 2nd generation Tri-Gate transistor technology [5] has been optimized for density, low power and wide dynamic range. 70 nm gate pitch, 52 nm metal pitch and 0.0499 um2 HDC SRAM cells are the most aggressive design rules reported for 14/16 nm node SoC process to achieve Moore's Law 2x density scaling over 22 nm node. High performance NMOS/PMOS...
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