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Software-based self-testing (SBST) is a well-known non-intrusive method for testing microprocessors. This paper presents a tool for automated Software-Based Self-Test program generation. The tool is based on the previously published methodology of using High-Level Decision Diagrams (HLDD) for modeling microprocessors and faults. The tool generates from the Instruction Set Architecture of the processor...
Due to the ongoing miniaturization of silicon technology beyond the sub-micron domain and the trend of integrating ever more components on a single chip, the Network-on-Chip (NoC) paradigm has emerged to address the scalability and performance shortcomings of bus-based interconnects. As the feature size shrinks, the system gets much more susceptible to faults caused by wear-out and environmental effects...
The main objective of this work is to develop a method and to create a tool for random test pattern generation for digital circuits, capable of achieving a high diagnostic resolution. We propose a measure for evaluating the diagnostic resolution of a given test set. Three methods were investigated using different criterions for selecting test patterns from the given packages of random vectors. The...
A new measure is proposed for evaluating multiple fault coverage of test sequences for microprocessor circuits. The class of faults under consideration includes gate-level Stuck-at-Faults (SAF), conditional SAF, and bridging faults of any multiplicity in control paths of microprocessors (MP). A new high-level functional control fault model for MP is introduced, and it is shown that 100% coverage of...
A new method of high-level test generation for control faults in digital systems is proposed. High-level faults of any multiplicity are assumed to be present, however, there is no need to enumerate them. A novel concept of test groups which has the goal to prove the correctness of a part of the system's functionality instead of keeping track of fault coverage during test generation as in the traditional...
A new method for high level fault modeling to improve the test generation for the control parts of digital systems was proposed. We developed a new high-level functional fault model based on High-Level Decision Diagrams (HLDD). It allows uniform handling of possible defects in different control functions related to instruction decoding, data addressing, and data manipulation. It was shown how the...
A new method of high level test generation based on the concept of test groups to prove the correctness of a part of system functionality is proposed. High-level faults of any multiplicity are assumed to be present in the system, however, there will be no need to enumerate them. Unlike the known approaches, we do not target the faults as test objectives. The goal of using the test groups is to extend...
Fault simulation is a critical tool in design, analysis of testability and verification of circuits. BDDs are a well-known model for manipulating Boolean functions. We propose a new type of BDD in the form of Shared Structurally Synthesized BDD (S3BDD) for representing the structure and simulating of faults in digital circuits. The paper offers a formula for calculating the minimal size, a method...
The paper presents a new structural fault collapsing method with linear algorithmic complexity to reduce the search space for test generation and fault diagnosis in digital circuits. The method is based on the two phase topology analysis of the circuit description. The first phase of fault collapsing is carried out on the gate level during superposition of Binary Decision Diagrams (BDD) of logic gates,...
We propose a very fast fault simulation method which is based on exact parallel critical path tracing developed for combinational circuits. To convert the sequential problem of fault simulation into the combinational one we introduce into the circuit a set of MISRs to improve the circuit's observability. The role of these MISRs is to monitor signals on the global feedback loops, and on selected fan-out...
The paper presents a novel approach to high-level fault modeling and test generation for microprocessors using High-Level Decision Diagrams (HLDD). A general frame-work and novel techniques for automated software-based self-test program generation are discussed. On this basis new previously not published test quality improvement capabilities of the approach are high-lighted and explained. Based on...
A method is proposed for simulating of transition delay faults (TDF) at different fault propagation conditions. The main idea of the method is to extend the TDF model, traditionally considered as a class of robustly tested delay faults, to a class of TDFs with extended detection conditions like non-robust and functional sensitization. A new sensitization type, called nonrobust functional sensitization...
A novel type of BDDs called Shared Structurally Synthesized BDDs (S3BDD) is presented for modeling sequential circuits for fault simulation purposes. The size of S BDD is in linear correlation with the circuit size and is characterized by the property of one-to-one mapping between the nodes in the graph and signal paths in the corresponding sequential circuit. A method is proposed for synthesis of...
A new method is presented for simulating of transition delay faults (TDF). The main idea of the method is to extend the TDF model, traditionally considered as a class of robustly tested delay faults, to a class of TDFs with extended detection conditions. Three known fault classes of delay fault sensitization are considered: robust, non-robust and functional sensitization of delay faults. Additionally,...
A new method for logic simulation and fault modeling in combinational circuits with Structurally Synthesized BDDs (SSBDD) is proposed. The new model is constructed by merging different super-graphs (SSBDDs) related to different circuit outputs, which share as much as possible different subgraphs (SSBDDs) representing the circuit. We call this model as Shared SSBDDs (S3BDD) where each node represents...
A new method of test generation based on the concept of partial test groups to prove the correctness of a combinational circuit is proposed. Stuck-at-faults (SAFs) of any multiplicity are assumed to be present in the circuit and we do not need to enumerate them. Unlike the known approaches, we do not target faults as test objectives. The goal is to verify by each test group the correctness of a selected...
Verification is increasingly becoming the bottleneck in designing digital systems. In fact, most of the verification cycle is not spent on detecting the occurrences of errors but on debugging, consisting of locating and correcting the errors. However, automated design-error debug, especially at the system-level, has received far less attention than error detection. Current paper presents an automated...
The paper presents an approach for integration of automatic test bench generation based on a hierarchical test pattern generator Decider into the high-level synthesis flow Abelite. While the high-level synthesis flow provides fast results of complex systems design, functional verification of the design including initial specification has remained until now a sophisticated manual process. The automatically...
We propose a hierarchical approach for the macro level cause-effect physical defect diagnosis in digital circuits. As macros we may consider arbitrary subcircuits or library components (e.g. complex gates) of digital circuits. The faulty macro location procedure is considered as a two step task. First, to locate a subset of suspected faulty macros in a network by using stuck-at-fault (SAF) dictionaries...
The paper introduces a novel constraint-based automated test pattern generator for Register-Transfer Level (RTL) designs. The tool combines test path constraint activation with a constraint solver. First, a deterministic algorithm that extracts constraints for activating test paths at RTL is applied. Subsequently, a constraint solving package ECLiPSe is used for assembling the tests. Experiments on...
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