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A novel and reliable rail-to-rail continuous-time Common-Mode Feedback Block (CMFB) circuit for low voltage, large output swing, and high-speed applications is presented in this paper. The main aims of the proposed idea are achieving high accuracy, high linearity and high-speed CMFB accompanied wideband dynamic range and large output swing as well. Hence, as MATLAB simulation results prove, employing...
In addition to the ESD characterization of unpowered integrated circuits, especially in the case of hard failures, an ESD characterization of powered ICs is necessary in order to analyze possible soft failures. Especially since these soft failures occur although ESD protection elements are used in the IOs/padframe. To analyze the different coupling paths in the ICs, in addition to a corresponding...
The paper presents the design and optimisation of memory buffer in the SALT (Silicon ASIC for LHCb Tracking) ASIC. The SALT is a new 128-channel readout ASIC for silicon strip detectors in the Large Hadron Collider beauty (LHCb) experiment at the Large Hadron Collider (LHC) in CERN. The stochastic nature of phenomena detected by the ASIC results in a very different amount of data after each collision...
Although standard 32/64-bit arithmetic is sufficient to solve most of the scientific-computing problems, there are still problems that require higher numerical precision. Multiple-precision arithmetic (MPA) libraries are software tools for emulation of computations in a user-defined precision. However, availability of a reconfigurable cards based on field-programmable gate arrays (FPGAs) in computing...
This paper describes the design of the transceiver, which is the implementation of the physical layer of EIA/TIA-485 standard. This circuit is a part of a more complex System on Chip designed in 130 nm CMOS technology. The problems encountered during the design process was described. The crucial issue was the relatively high voltage range, from −7 V to 12 V, that may appear on the pins of the SoC...
Atrial fibrillation (AF) is the most common arrhythmia and it occurs in strict correlation with the patients' age. AF is a known risk factor of ischemic stroke (ISC), which is considered as one of the major causes of death and disability and pays the essential contribution to health system costs. The paper presents the idea and practical implementation of a long-term non-invasive instrumentation for...
Measuring, monitoring and analysis of dynamic movements in sports during a real-time competition is becoming more important than ever. Many methods used currently may only be applied in the artificial environment of a laboratory. Other methods require too much processing to be used efficiently in real-time. Interesting opportunity for these problems gives acceleration measurements and their usage...
Wireless data transmission dominates the total power consumption of implanted multichannel neural recording system. However, it can be significantly reduced by using on-chip data compressor. It has been found that Discrete-time wavelet transform (DWT) is a very effective tool for compressing neural data. Therefore, in this paper a wavelet-based data compressor suitable for multichannel implanted neural...
The CloudBus protocol is one of the methods which is used for data exchange and concurrent process synchronization in the distributed embedded systems. It realizes decentralized (distributed) control method, where each node is equal to each other. This communication model allows the significant savings in the amount of transmitted data between end modules. However, there are many distributed embedded...
Modern power systems have to ensure the quality of power supply in spite of the rapid changes of power consumption. Choosing the appropriate parameters of the transfer function of the digital control circuit of the converter main block is especially important. The most common method of obtaining the discrete transfer function of control circuit is an analog prototype. An important problem is the accurate...
This paper summarizes the work performed by the authors on development of the sensor network for thermal parameters measurements, as well as structure health monitoring in modern buildings. The described work was carried out as a part of a workpackage within the EC FP7 project SESBE.
REuP (REconfigurable microprocessor) is a concept of instructionless general purpose reconfigurable processor. Such architecture implies that any functionality can be achieved through a variety of solutions not necessarily equivalent to typical CPU implementation, thus application based tests are required to provide its overall performance. The paper presents optimized implementation of TwoFish encryption...
The strict characteristic and the comparative analysis of the developed by authors the coherent and the component methods for statistical analysis of periodically correlated random processes (PCRP) — the mathematical models of the stochastic oscillations — for unknown period of the non-stationarity is given. The comparison of efficiencies of the proposed methods for period estimation with the given...
This paper presents a technique intended to reduce the power to transmit data, suitable for implanted biomedical wireless sensors. The signal acquired from an implantable sensor may receive some analog processing (filtering, amplification, linearization) and is AD converted for transmission. In low power applications, the conversion uses voltage to frequency converter (VFC). We propose an energy approach...
In this paper, we propose a high precision vernier type delta-sigma time to digital converter (TDC) architecture. The time resolution of conventional delta-sigma TDC that has a delay stage consists of a delay element and three multiplexers is strongly dependent on the delay time for a delay element used in the delay stage and the measurement time. However, the delay time is limited by the complementary...
We propose a simple current reference circuit with low power supply voltage dependence and low temperature coefficient by combining output currents of conventional current mirror and Nagata current source. Detailed analysis and design procedure are presented. Preliminary test chip measurement results are also represented. Temperature dependence of the output current was compensated by synthesizing...
We proposed a linearization technique with dynamic element matching for stochastic flash A-to-D converters (SFADCs), and estimated that 6-bit SFADC can be realized by using about 1,000 comparators through system level simulations. In this paper, we present circuit level design of the linearized SFADC. First, we discuss the difference between requirements of comparators for conventional flash ADC and...
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