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In This paper, a reconfigurable CMOS folded cascode LNA for multi-standard wireless applications is presented, including GSM (PCS1900), 3G (UMTS), Bluetooth and WLAN b/g. Based on inductive degenerated folded-cascode topology for low voltage applications, the proposed LNA achieves a good trade-off between good gain, noise figure and power consumption. The input and output matching networks include...
Modular exponentiation is the key operation in public key cryptosystems such as RSA (Rivest, Shamir Adelman). It is implemented by repeated modular multiplications which are time consuming for large operands. Accelerating RSA requires reducing the number of modular multiplications with speeding up the modular multiplication. In this paper, we present a high throughput architecture implementing a fast...
Current innovations in electronics combine performance, size and cost criteria. Nevertheless, in the all-digital era, the 2D technology and the fabrication of CMOS Integrated Circuit are approaching their ultimate limits. As a result, the use of 3D technology in the fabrication of different Integrated Circuits becomes very appealing. Among the aspects of the 3D Integration we find the Through Silicon...
SoC Verification is one of the hot issues in VLSI. More than 70 percent of the time is spent on verification. So, there is a need for constructing a reusable and robust verification environment. Universal verification methodology (UVM) is a promising solution to address these needs. This paper presents a survey on the features of UVM. It presents its pros, cons, and opportunities. Moreover, it presents...
Due to timing variations induced by process variations and environmental effects, speedpath debugging becomes a major concern in the design of high performance VLSI circuits. In this paper, we propose an efficient approach to speedpath debugging based on Boolean Satisfiability (SAT). We use a time-discrete model of the circuit for analyzing effects of delays within the circuit. For efficiency we overapproximate...
A novel type of BDDs called Shared Structurally Synthesized BDDs (S3BDD) is presented for modeling sequential circuits for fault simulation purposes. The size of S BDD is in linear correlation with the circuit size and is characterized by the property of one-to-one mapping between the nodes in the graph and signal paths in the corresponding sequential circuit. A method is proposed for synthesis of...
This article takes a first step in the field of secured circuits testing and characterization of associated fault models. We analyze the electrical impact of the resistive bridge defect in deep-submicron secured circuits, implemented in WDDL and in SecLib. The quality of this analysis is verified by SPICE simulations. It is shown that the detection of defect depends on the bridging resistance value...
Nanostructured porous silicon is very promising for RF applications by overcoming the high-frequency losses originating from the bulk silicon substrate. RF performance and non-linearity analysis of different silicon substrates including, porous (PSi), trap-rich (TR) high resistivity (HR) types are explored experimentally. The investigation is done by means of coplanar transmission lines (CPW) fabricated...
In the last decade, academies and private companies have actively explored emerging memory technologies. STT-MRAM in particular is experiencing a rapid development but it is facing several challenges in terms of performance and reliability. Several techniques at cell level have been proposed to mitigate such issues but currently few tools and methodologies exist to support designers in evaluating...
A fixed-point ASIC design for high-speed, second-order, piecewise function approximation is presented. A Non-Uniform segmentation method based on Minimax approximation is used to get the interpolation coefficients. Non-Uniform segmentation, effectively, reduces the size of the coefficient table with a small area overhead for the address encoder. The proposed algorithm truncates the binary coefficients...
The need for wideband data converters (DAC and ADC) with increasingly higher sampling frequencies and data resolutions are driven by new applications, as well as advances in existing ones. The bandwidth limitations of current I/O technologies, such as CMOS or LVDS, force the need for higher pin counts on converter products. The JESD204 standard interface offers several advantages over its CMOS and...
One of the best know examples of integration of spintronic devices with CMOS is given by MRAM (magnetic random access memory), a digital memory where each node in its simplest form includes a switching element (transistor) in series with a magnetic tunnel junction (magnetic storage element). In the analog field, work is beginning in the design, fabrication, and back end integration of ASICS with magnetic...
A significant portion of mixed-signal integrated systems is already used in safety-critical applications, such as transportation. It has often to operate under harsh environmental conditions for a long time (aging). One example is car electronics for the future generation of drive-by-wire. As a result the electronics used here has to be resilient for aging.
Software implementation of compute-intensive applications in digital signal processing requires large computing power and has real-time performance requirements. Employing multicore architecture is usually the only means for solving the grand challenge of computational problems. Developing multicore-based systems requires a high degree of concurrency for optimizing performances of systems. For this...
This paper addresses the problem of optimal hardware-realization of finite-word-length (FWL) linear controllers dedicated to MEMS applications. The biggest challenge is to ensure satisfactory control performances with a minimal hardware. To come up, two distinct but complementary optimizations can be undertaken: in control theory and in binary arithmetic. Only the latter is involved in this work....
We are quickly reaching an impasse to the number of transistors that can be squeezed onto a single chip. This has led to a scramble for new nanotechnologies and the subsequent emergence of new computing architectures capable of exploiting these nano-devices. The memristor is a promising More-than-Moore device because of its unique ability to store and manipulate data on the same device. In this paper,...
Embedded instruments are becoming used more often in modern SoCs for different testing and measurement purposes. IEEE 1687 (iJTAG) is a newly IEEE approved draft standard for embedded instruments access and control based on the widespread IEEE 1149.1 TAP port. In this paper the work done for enabling iJTAG control, observation and reconfiguration of complex digital embedded instruments will be discussed...
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