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The number of memory components in today's chips is increasing considerably. Through the limitations on area and number of test pins, it is not feasible to use a separate BIST architecture for testing every memory on the chip. Therefore, it is essential to have a configurable BIST architecture. In this paper, a configurable memory BIST architecture that can test different memories having different...
This paper presents a method to design a kind of power supply (PS) using PID (Proportional, Integral, and Derivative) controller. AVR microcontroller, atmega16 has been used in designing PS. Nowadays most of industrials systems use microcontrollers. PS is the integral part in each of them. A good idea is using these processors in order to generate the needed power for other parts of the systems. Especially...
The paper presents an approach for integration of automatic test bench generation based on a hierarchical test pattern generator Decider into the high-level synthesis flow Abelite. While the high-level synthesis flow provides fast results of complex systems design, functional verification of the design including initial specification has remained until now a sophisticated manual process. The automatically...
This paper presents definitions characterizing the concepts regarding cyber-physical systems and dependability. Cyber-physical systems incorporate computing, communication and storage capabilities with monitoring and/or control of entities in the physical world in a dependably, securely, efficiently and real-time way. The challenges of cyber-physical system research are concerning: real-time system...
This paper presents a solution for the Wi-Fi reconfiguration of FPGAs. A design that manages the reconfiguration process of a Xilinx Spartan-3 FPGA by using a Wi-Fi Tag4M device that receives reconfiguration data wirelessly from a Configuration Server was developed. This research is especially important for adding self-healing capabilities to large and complex digital systems.
It is costly to have defective networks and nodes. There are many factors involved in the cost of defective design of networks. The size of development team, stage of development when the defect occurs, routing protocols and subtlety of the defect are only a few of the possibilities. Testing software, therefore has to be designed to detect the defect, and as early as possible in the design cycle....
The paper presents a new unifying formalism introduced to effectively support the automatic generation of assembly test programs to be used as SBST (Software Based Self-Testing) for both data and instruction cache memories. In particular, the new formalism allows the description of the target memory, of the selected March Test algorithm, and the way this has to be customize to adapt it to the selected...
Simulation-based verification is a widely-spread approach to ensure functional correctness of hardware designs [1,2]. It is usually done by co-simulating a design under verification with an independently created reference model and checking conformance of their reactions. To reduce verification expenses, abstract models are commonly used (they are simpler, less error-prone and more reusable). Design...
In this paper a programmable highly linear voltage-to-current conversion technique for low noise, wide tunable frequency range voltage controlled oscillator (VCO) is presented. The effect of VCO gain on phase locked loop (PLL) phase noise and frequency stability characteristics is addressed. The proposed solution offers digital calibration of VCO gain and frequency, using binary weighted thick oxide...
The paper considers the processing of constant modulus signals in multi-beam adaptive arrays. The processing is based on the substitution of multi-extreme cost-function of the adaptive filtering process by a linearly constrained quadratic one and the decomposition of the signal processing algorithm for multi-beam array on a number of separate algorithms, related to each sub-array. The simulation demonstrates...
The method of hardware reduction is proposed which is oriented on compositional microprogram control units with code sharing and PAL-based CPLD chips. The method is based on a wide fan-in of PAL macrocells allowing using more than one source for codes of operational linear chains. An example of the proposed method application is given.
The method of decrease in the number of PAL macrocells in logic circuit of Moore finite-state-machine (FSM) is proposed. Some peculiarities of Moore FSM such as existence of pseudoequivalent states and dependence of output functions on states as well as a wide fan-in of PAL macrocells are used to optimize the hardware amount (the number of PAL macrocells). It allows hardware amount decrease without...
This article describes an infrastructure and technologies for analyzing information space, based on virtual cybercomputer. A model and metrics for cyberspace, where subjects are the interacting processes or phenomena with the physical carrier in the form of computer systems and networks, are proposed. The structural model of high-speed multimatrix processor designed for fast and accurate search of...
Xor-metrix for object relations in a vector logic space and a structural testing model are proposed. Assertion-based models and methods for the verification and diagnosis of HDL-code functional failures, which make possible to reduce considerably time-to-market of software and hardware, are developed. An architectural model of multimatrix reduced logical instruction set processor for embedded diagnosing...
This article describes an infrastructure and technologies for diagnosis. A transactional graph model and method for diagnosis of digital system-on-chip are developed. They are focused to considerable decrease the time of fault detection and memory for storage of diagnosis matrix by means of forming ternary relations in the form of test, monitor, and functional component. The following problems are...
High reliability and nonvolatile antifuse technology make Actel RTAX-S the FPGA of choice for space designers. As correct functionality of such designs is crucial, prototyping becomes an important step of the verification flow. As RTAX-S FPGAs are one-time programmable, prototyping can become challenging. This paper provides an overview and comparison of the existing approaches to prototyping of Actel...
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