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The ARTEMIS 1 project DEWI ("Dependable Embedded Wireless Infrastructure") focusses on the area of wireless sensor / actuator networks and wireless communication. With its four industrial domains (Aeronautics, Automotive, Rail, and Building) and 21 clearly industry-driven use cases / applications, DEWI will provide and demonstrate key solutions for wireless seamless connectivity and interoperability...
This paper compares two types of physical unclonable function (PUF) circuits in terms of reliability, mismatch-based PUF vs. physical-based PUF. Most previous PUF circuits utilize device mismatches for generating random responses. Although they have sufficient random features, there is a reliability issue that some portions of bits are changed over time during operation or under noisy environments...
Gaining better insights into propagation and masking of radiation induced faults at some point requires the conduction of physical experiments. In our attempt to design a target ASIC for such experiments we elaborated an on-chip infrastructure that allows recording the pulse width of radiation induced voltage transients. Its unique properties are the ability to record more than one of these measurement...
We study three-level implementations where the first two levels represent a standard PLA form with an ANDplane and an OR-plane. This implements a 2m-output SOP. The final stage consists of m two-input programmable LUTs. The PLA outputs are paired so that the LUT outputs implement a set of m given incompletely specified functions (ISFs). Three-level structures have been studied previously, e.g. resulting...
The increasing adoption of multi-core Systemson-Chip (SoC) in critical systems has turned security into an important design requirement. In addition to making a SoC tamper-resistant by embedding cryptographic solutions, in order to make a system robust, we need to control the level of access to the critical functions and capabilities. We propose a hardware protection architecture to enhance a traditional...
The FSM-SADF model of computation allows to find a tight bound on the throughput of firm real-time applications by capturing dynamic variations in scenarios. We explore an FSM-SADF programming model, and propose three different alternatives for scenario switching. The best candidate for our CompSOC platform was implemented, and experiments confirm that the tight throughput bound results in a reduced...
Solving complex optimization problems with genetic algorithms (GAs) with custom computing architectures is a way to improve the execution time of this metaheuristic, which is known to consume considerable amounts of time to converge to final solutions. In this work, we present a scalable computing array architecture to accelerate the execution of cellular GAs (cGAs), a variant of genetic algorithms...
The Feed In Tariff policy (FIT) used for accelerating renewable energy investments cannot be retained as a sustainable business model for the future smart energy grid. It is also evident that the current centralized electricity market prevents small or very small energy producers, who usually generate energy by renewable means, to participate. In this paper, addressing the aforementioned problems,...
Physical attacks, such as fault attacks, pose a decisive threat for the security of devices in the Internet of Things. An important class of countermeasures for fault attacks is fault tolerant software that is applicable for systems based on COTS hardware. In order to evaluate software countermeasures against fault attacks, fault injection is needed. However, established fault injection approaches...
Explicitly managed memories have emerged as a good alternative for multicore processors design in order to reduce energy and performance costs. Memory transfers then rely on Direct Memory Access (DMA) engines which provide a hardware support for accelerating data. However, programming explicit data transfers is very challenging for developers who must manually orchestrate data movements through the...
A new method for the minimization of finite state machines (FSMs) is proposed. In this method, such optimization criteria as the power consumption and possibility of merging other states are taken into account already at the stage of minimizing internal states. The method is based on sequential merging of two internal states. For this purpose, the set of all pairs of states that can be merged is found,...
The Energy Internet is the vision of performing intelligent automation in the smart grid using Internet-based technologies. This vision complies with embracing the residential domain into the smart grid, since it facilitates the reuse of the existing Internet connection in the home. Stakeholders such as Energy Service Companys (ESCOs) and Distribution System Operators (DSOs) can then acquire meter...
Execution time is no longer the only performance metric for computer systems. In fact, a trend is emerging to trade raw performance for energy savings. Techniques like Dynamic Power Management (DPM, switching to low power state) and Dynamic Voltage and Frequency Scaling (DVFS, throttling processor frequency) help modern systems to reduce their power consumption while adhering to performance requirements...
The paper presents a new structural fault collapsing method with linear algorithmic complexity to reduce the search space for test generation and fault diagnosis in digital circuits. The method is based on the two phase topology analysis of the circuit description. The first phase of fault collapsing is carried out on the gate level during superposition of Binary Decision Diagrams (BDD) of logic gates,...
Despite the perceived lightweight and structural regularity of Arbiter PUF (APUF), high quality (bias -- free) large APUF implementation on FPGA has traditionally proved to be challenging. Currently, the most widely accepted design approach for FPGA -- based APUF implementation is the Programmable Delay Line (PDL) based APUF. In this work, we describe a scalable design methodology to implement close-to-ideal...
A Ring Oscillator (RO) integrated in a design can be used for detecting insertion of malicious logic i.e., a hardware Trojan horse. Recently, the Transition Effect Ring Oscillator (TERO) was proposed as a means for implementing True Random Number Generators (TRNGs) and Physically Uncloneable Functions (PUFs). In this paper, we explore the timing sensitivity of TERO against RO, towards introducing...
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