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In this brief, we model system-on-chip consumption as a dynamic process that can be easily tracked over time through a set of power modes. The proposed method provides precise information on each block dissipation inside the system. Each generated mode defines a specific model that links power to block activity reported by a set of critical signals. The modeling approach is illustrated by real experiments...
In this paper we propose a strategy for better exploiting Multi-Processor Systems-on-Chip resources utilization by means of using a control-loop feedback mechanism. We apply the proposed techniques in a purely distributed memory MPSoC architecture that is composed of a frequency scaling module responsible for tuning the frequency of processors at run-time. Results show very promising in terms of adaptation...
The increasing failure rates observed in very deep sub micron silicon technologies pose a major problem to the design of future high-density SoCs. Emerging new architecture based on Multiprocessor SoC (MPSoC) gives the opportunity to exploit the natural redundancy with replicated spare processor in order to maintain the system performance in presence of failures. Based on the assumption that a transient...
The complexity of MP2SoC architectures to come is such that many issues arise simultaneously, such as multicore programming, system performance, reliability, scalability, etc. The key to solve these issues is self-adaptability: the chips to come have to integrate the required software and hardware means to monitor and self-react to the various kinds of events that are likely to occur during chip's...
We will present a survey of trends in the semiconductor industry for programmable hardware. The main objective of this paper is educational and the focus is FPGAs and its related or vs technologies which have emerged mostly in the second half of the last decade. We will try to analyze what were the prominent reasons for emerging of these technologies. What are the advantages and drawbacks of them,...
In this paper we propose an adaptive technique to reduce power consumption of Multiprocessor Systems-on-Chip. The method, based on Game Theory, optimizes the frequencies of local processors while fulfilling applicative real-time constraints. Contrary to other approaches, our solution is compatible with reconfigurable Systems-on-Chip. The obtained power consumption gains on a telecommunication test-case...
In this paper we present an adaptive technique to locally adjust the frequency of processing elements on MP-SoC. The proposed method, based on game theory, optimizes the system while fulfilling dynamic constraints. A telecom test-case has been used to demonstrate the effectiveness of our technique. For the evaluated scenario, the proposed technique has obtained up to 20% of latency gain and 38% of...
Multiprocessor system-on-chip composed of several processing elements will be integrated in embedded systems handling multiple applications with diverse constraints. In order to improve the system performance and temperature profile, dynamic voltage frequency scaling can be applied at processor level. In this article we study an existing approach based on Game Theory, which adjusts at run-time the...
We consider multiprocessor system-on-chip (MP-SoC) integrating several processing elements (PE). These architectures require distributed and scalable control techniques for run-time optimization of applicative parameters. Our approach is to use the game theory as an optimization model to solve the trade-off issues at run-time. We applied it to the distributed dynamic voltage frequency scaling (DVFS)...
In this article, we present an original MPI-based adaptive task migration support for the HS-Scale system. Our previous communication API was modified in order to be MPI compliant. In order to enable task migration without any MMU, a Position Independent Code compilation technique is implemented. The self-adaptability is based on monitoring information collected at run-time by each processing element...
With forecasted hundreds of processing elements (PE), future embedded systems will be able to handle multiple applications with very diverse running constraints. In order to avoid hot-spots and control the temperature of the tiles, dynamic voltage-frequency scaling (DVFS) can be applied at PE level. At system level, it implies to dynamically manage the different voltage-frequency couples of each PE...
Scalability of architecture, programming model and task control management will be a major challenge for MP-SOC designs in the coming years. The contribution presented in this paper is HS-Scale, a hardware/software framework to study, define and experiment scalable solutions for next generation MP-SOC. The hardware architecture, H-Scale, is a homogeneous MP-SOC based on RISC processors, distributed...
Nonvolatile flash memories are becoming more and more popular in systems-on-chip (SoC). Embedded flash (eFlash) memories are based on the well-known floating-gate transistor concept. The reliability of such type of technology is a growing up issue for embedded systems; endurance and retention are of course the main features to analyze. To enhance memory reliability current eFlash memories designs...
Non-volatile embedded Flash (eFlash) memories are very popular in Systems-on-a-Chip (SoC). These memories are based on the well-known floating gate concept. While densities and quality constraints are increasing, the reliability becomes a growing up issue. For eFlash memories, endurance and retention issues are at the root of reliability losses. To improve reliability, eFlash memories designs usually...
This work addresses the problem of hardware attacks against cryptographic circuits. The most dangerous side-channel attack: the differential power analysis (DPA) is discussed, as well the state of art countermeasures. Then new reconfigurable system on chip resistant against DPA attacks is proposed. Results shows that our architecture is efficient against DPA attacks, but also outcomes the performance...
This paper describes an engine, called PE-ICE (parallelized encryption and integrity checking engine), enabling to guarantee the confidentiality and the integrity of data exchanged between a SoC (system on chip) and its external memory by using an existing block-encryption algorithm. Performance evaluations show that the overhead of security mechanisms in PE-ICE remains low (below 12%) compared to...
This paper describes a novel engine, called PE-ICE (parallelized encryption and integrity checking engine), enabling to guarantee confidentiality and integrity of data exchanged between a SoC (system on chip) and its external memory. The PE-ICE approach is based on an existing block-encryption algorithm to which the integrity checking capability is added. Simulation results show that the performance...
This paper describes a novel engine, called PE-ICE (parallelized encryption and integrity checking engine), enabling to guarantee the confidentiality and the integrity of data exchanged between a SoC (system on chip) and its external memory by adding the integrity checking capability to a block encryption algorithm
Dynamic reconfiguration provides interesting features offering hardware flexibility and adaptability. Unfortunately, the lack of programming tools to manage it has limited its use in current SoCs. This paper presents a method to abstract, at design-time, dynamic reconfiguration management. Dynamic hardware multiplexing is a generic principle based on a scheduler dedicated to reconfigurable resources...
A homogeneous architecture made of an array of so-called NPUs (network processing units) is presented in this paper. Those NPUs are endowed with elementary processing and communication capabilities, that for exploring the opportunity of finely adapting system behavior according to current system state. Applications considered in this work are described as task graphs, which are mapped at run-time...
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