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Designing a universal embedded hardware architecture for discrete wavelet transform (DWT) is a challenging problem due to the diversity among wavelet kernel filters. In this work, we present three different hardware architectures for implementing multiple wavelet kernels. The first scheme utilizes fixed, parallel hardware for all the required wavelet kernels whereas the second scheme employs a processing...
We compare two approaches for high-level power estimation of DSP components implemented in FPGAs for different sets of data streams from real-world applications. The first model is a power macro-model based on the Hamming distance of input signals. The second model is an analytical high-level power model based on switching activity computation and knowledge about the component's internal structure,...
This paper presents optimized implementations of two different pipeline FFT processors on Xilinx Spartan-3 and Virtex-E FPGAs. Different optimization techniques and rounding schemes were explored. The implementation results achieved better performance with lower resource usage than prior art. The 16-bit 1024-point FFT with the R22SDF architecture had a maximum clock frequency of 95.2 MHz and used...
A well defined target architecture is essential to the success of high-level partitioning and synthesis tools. We present DINAMO, an architectural model tailored for distributed implementations of discrete signal transforms (DSTs) such as FFTs and discrete cosine transforms. DINAMO is a modular generalization of horizontal/vertically folded computational structures, common in fast versions of DSTs...
This paper presents an embedded FPGA-based architecture to compute navigation trajectories along a harmonic potential. The goals and obstacles may be changed during computation. Large environments are split into blocks. This approach, together with the use of an increasing precision, enables an optimization of the overall computation time that is theoretically and experimentally studied. Implementation...
Confidentiality and integrity of bitstreams and authenticated update of FPGA configurations are fundamental to trusted computing on reconfigurable technology. In this paper, we propose to provide these security services for digital content broadcast to FPGA-based devices. To that end, we introduce a new property we call forward security, which ensures that broadcast content can only be accessed by...
We present a fast, efficient, and parameterized modular multiplier and a secure exponentiation circuit especially intended for FPGAs on the low end of the price range. The design utilizes dedicated block multipliers as the main functional unit and block-RAM as storage unit for the operands. The adopted design methodology allows adjusting the number of multipliers, the radix used in the multipliers,...
Many digital communications algorithms present characteristics that make very difficult to implement them in either a software solution or as a fully custom hardware architecture. Their inherent complexity implies two challenges at the same time: to process the information as fast as possible to present the results when they are required, and to build a system that meets the power consumption and...
In many applications, subsequent tasks differ only in a specific set of parameters. Because of their reconfigurability, FPGAs (field programmable gate arrays) can be configured with an optimized configuration every time these parameter values change. This results in configurations that are smaller and faster than their generic counterparts. Unfortunately, the overhead involved in generating these...
Biological sequence alignment is an essential tool used in molecular biology and biomedical applications. The growing volume of genetic data and the complexity of sequence alignment present a challenge in obtaining alignment results in a timely manner. Known methods to accelerate alignment on reconfigurable hardware only address sequence comparison, limit the sequence length, or exhibit memory and...
This paper describes the hybrid architecture developed for speeding up the processing of so-called multi-modal visual primitives which are sparse image descriptors extracted along contours. In the system, the first stages of visual processing are implemented on FPGAs due to their highly parallel nature whereas the higher stages are implemented in a coarse parallel way on a multicore PC. A significant...
FPGA based implementations of two classes of pseudo random number(PRN) generator, intended for use in Monte Carlo methods for finance, are presented. FPGA implementations potentially offer reduced cost and improved performance compared to general purpose processor (GPP) systems such as PCs or mainframes. The first class of PRN generator, which includes the mersenne twister, uses generalized feedback...
Modern applications require powerful high-performance platforms to deal with many different algorithms that make use of massive calculations. At the same time, low-cost and high-performance specific hardware (e.g., GPU, PPU) are rising and the CPUs turned to multiple cores, characterizing together an interesting and powerful heterogeneous execution platform. Therefore, self-adaptive computing is a...
Reconfigurable hardware can be used to build a multi-tasking system where tasks are assigned to HW resources at run-time according to the requirements of the running applications. These tasks are frequently represented as direct acyclic graphs and their execution is typically controlled by an embedded processor that schedules the graph execution. In order to improve the efficiency of the system, the...
In this paper a low level vision processing node for use in existing IEEE 1394 camera setups is presented. The processing node is a small embedded system, that utilizes an FPGA to perform stereo vision preprocessing at rates limited by the bandwidth of IEEE 1394a (400 Mbit). The system is used in a hybrid architecture [5], where it produces undistorted and rectified 512 x 512 images at 2 x 15 frames...
A design approach for multiprocessor systems on FPGAs is presented. The goal is to customize such systems for target parallel programs by simultaneously solving the problems of task mapping and high level synthesis. By considering the effect of fixed-priority preemptive scheduling when several tasks share a processor resource, a broad spectrum of embedded application requirements is covered. Experimental...
Nowadays hi-tech secure products offer more services and more security. The corresponding market is now oriented towards more flexibility. As an answer we propose here a multi-algorithm cryptographic co-processor called Celator. A main processor entrusts to the Celator the cryptographic tasks like encrypting or decrypting data blocks using secret key encryption algorithms such as advanced encryption...
Power analysis is an important and efficient mean for side channel attacks on security applications. By monitoring devices' power consumption during various operations it is possible to collect security information (e.g. the encryption key). These power drop-offs counter effects could be reduced or even eliminated, if accurate power estimations could be achieved on the early design cycles. It is crucial...
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