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To increase the amount of logic available in SRAM-based FPGAs manufacturers are using nanometric technologies to boost logic density and reduce prices. However, nanometric scales are highly vulnerable to radiation-induced faults that affect values stored in memory cells. Since the functional definition of FPGAs relies on memory cells, they become highly prone to this type of faults. Fault tolerant...
Microfluidics-based biochips are revolutionizing laboratory procedures involving molecular biology. Advances in microfluidics technology offer exciting possibilities for high-throughput DNA sequencing analysis, protein crystallization, drug discovery, immunoassays, and environmental toxicity monitoring. Another emerging application area for microfluidics-based biochips is clinical diagnostics, especially...
In this work a co-synthesis method, which allows for optimization of dynamically self-reconfigurable SOPC system architecture, is presented. Partially reconfigurable FPGAs let better use hardware resources due to reuse of the same parts of the chip for different functionalities in the same application. The algorithm maximizes speed of the SOPC system taking into consideration FPGA's area constraints...
The inter-die and intra-die variations in process parameters (in particular, threshold voltage (Vt)) can lead to large number of failures in an SRAM array, thereby, degrading the design yield in nanometer technologies. To improve parametric yield of nano-scaled memories, different circuit and architectural level techniques can be used. In this paper, we first analyze and model different SRAM failures...
Rapid advances of semiconductor technology lead to higher circuit integration as well as higher operating frequencies. The statistical variations of the parameters during the manufacturing process as well as physical defects in integrated circuits can sometimes degrade circuit performance without altering its logic functionality. These faults are called delay faults. In this paper we consider the...
Phase-locked loops (PLLs) are used to implement a variety of timing related functions such as frequency synthesis, clock and data recovery, and clock de-skewing. Any jitter or phase noise in the output of the PLL used in these applications generally degrades the performance margins of the system in which it resides and so is of great concern to the designers of such systems. Jitter and phase noise...
This paper describes a new self-testing 1-bit full adder. This circuit consists of three polymorphic NAND/NOR gates, two XOR gates and two inverters. The adder is able to detect a reasonable number of stuck-at-faults without the need of any additional logic and diagnostic signals. A fault is indicated by oscillations at the carry-out output. Properties of n-bit carry-propagate adder which is composed...
The paper presents a general approach for partitioning optimization based on the hierarchical clustering by the optimal circuit reduction (OCR) method. This method has proved to be robust, effective and efficient tool to identify the hierarchical clusters circuit structure. For initial partitioning and its optimization the optimal circuit reduction trees are used. Recursive moves (transfers and exchanges)...
Logic soft errors caused by radiation are a major concern when working with circuits that need to operate in harsh environments, such as space or avionics applications, where soft errors are traditionally referred as single event effects. In this paper, system knowledge-based hardening techniques using recursive structures for the implementation of moving average filters that provide protection against...
Time-to-digital converter designing and analysis for asynchronous ADCs is discussed in the paper. The proposed ADC utilizes two-level conversion scheme consisting in duty-cycle modulation and subsequent time-to-digital conversion (TDC). Three concepts of the asynchronous ADC digital serial output interface are presented. The comparison of minimum transmission rates of the serial output port(s) for...
This paper addresses an efficient concurrent fault detection scheme for the SBox hardware implementation of the AES algorithm. Concurrent fault detection is important not only to protect the encryption/decryption process from random and production faults. It will also protect the system against side-channel attacks, in particular fault-based attacks, i.e. the injection of faults in order to retrieve...
Highly parallel architecture for local histogram equalisation is studied. Three different kinds of approaches to the parallel architecture are regarded in this paper. (1) Module-level -which focuses on processing as many data as possible within a single module. (2) 1D -Several modules conducting simultaneously histogram equalization on partially overlapping (either horizontally or vertically) frames...
Algorithmic State Machines are a 40-year old tool for the design of digital circuits. They are a good alternative to finite state machines, where only states can be properly described, but actions must be annotated as lateral comments. However, current notation for these diagrams has several limitations for medium-large designs, and often lateral annotations are finally needed. This paper presents...
Modern FPLD devices have a very complex structure. They combine PLA-like structures as well as FPGA's and even memory-based structures. However, the lack of an appropriate synthesis method does not allow the features of the modern FPLD's to be fully exploited. In this paper, an important problem of state assignment for an FSM as an extension of the previous research on ROM-based FSM implementation...
A low noise and low power CMOS image sensor (CIS) with pixel-level correlated double sampling (CDS) is proposed. As the pixel readout circuit using source follower is major readout noise and power consumption source in the conventional CIS structure, the proposed new structure removes the source follower and performs pixel-level CDS and comparing. The proposed CIS is integrated with 240 times 180...
Memory is a significant performance limiting factor of the multiprocessor systems especially when shared. In FPGAs, the memory amount of the device is fixed and thus, optimal memory usage is essential. This paper analyses how the fixed amount of memory should be divided between instruction memories and instruction caches for multiprocessor systems and compromised with the number of processors. The...
The aim of this paper is to present a simple, lightweight, multi-threaded network processor core implemented in a FPGA circuit 1. The authors prove that it is possible to design a processor core with hardware switched threads in a FPGA integrated circuit efficiently. The details of the processor core's architecture are described. The compilation results prove, that the proposed core is able to run...
A proposal for a new system to capture signals in the optical module (OM) of an underwater neutrino telescope is described. It concentrates on the problem of power consumption and the time precision. In particular, a solution for the interface between the photomultiplier (PMT) and the front-end electronics is presented.
Increasing level of process variation in the sub-100 nm silicon technology is becoming an important issue. In this paper we describe an approach to estimate the impact of process variations on the static CMOS and the dual-rail PLA down to 32 nm process. This approach is built on accurate variation modeling, published data including the ITRS, Predictive Technology Models, and Monte-Carlo analysis....
As yield improvement becomes more important the differences between the modeled faults and actual defects in the diagnostic simulation process gets in the way. The need to diagnose the failure mechanisms closer to reality is driving the test industry towards more accurately modeling of defects as much as possible. Most failures occur as shorts and opens. Bridging faults represent shorts much more...
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