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In this paper we propose a new communication synthesis approach targeting systems with sequential communication media (SCM). Since SCMs require that the reading sequence and writing sequence must have the same order, different transmission orders may have a dramatic impact on the final performance. However, the problem of determining the best possible communication order for SCMs is not adequately...
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based global optimization algorithm to generate the nominal Pareto front efficiently using a simulator-in-a-loop approach. The solutions on this Pareto front combined with efficient Monte Carlo approximation ideas are then used...
The impact of process variation on SRAM yield has become a serious concern in scaled technologies. In this paper, we propose a methodology to analyze the stability of an SRAM cell in the presence of random fluctuations in the device parameters. We provide a theoretical framework for characterizing the DC noise margin of a memory cell and develop models for estimating the cell failure probabilities...
In this paper, we propose a novel methodology for statistical SRAM design and analysis. It relies on an efficient form of importance sampling, mixture importance sampling. The method is comprehensive, computationally efficient and the results are in excellent agreement with those obtained via standard Monte Carlo techniques. All this comes at significant gains in speed and accuracy, with speedup of...
The fabless model was traditionally enabled through clean interfaces oth in technical and business terms - between foundries and fabless semiconductor companies. However, with advanced geometry and analog/mixed-signal process nodes, the technical challenges have been greatly magnified, so that successful semiconductor design requires intimate co-optimization of design and manufacturing, infringing...
Since performance on FPGAs is dominated by the routing architecture rather than wire length, we propose a new architecture-aware approach to initial FPGA placement that models the relationship between performance and the routing grid, using concepts from graph embedding and metric geometry. Our approach, CAPRI, can be viewed as an embedding of a graph representing the net list into a metric space...
In this paper, we present a generic interconnect fabric for transaction level modelling tackeling three major aspects. First, a review of the bus and 10 structures that we have analysed, which are common in todays system on chip environments, and require to be modelled at a transaction level. Second our findings in terms of the data structures and interface API's that are required in order to model...
This paper describes the design methodology, simulation, and tools used to design a 4.25 Gb/s high output swing laser driver (LD) and the electrical to optical interface from the LD to the laser diode. The quality of the optical output of a fiber optic communication channel is mainly determined by the LD and the electrical interface from the LD to the laser diode. Of particular importance in the interface...
Simulation and verification using electronic design automation (EDA) tools are key steps in the design process for communication and signal processing systems. The synchronous dataflow (SDF) model of computation is widely used in EDA tools for system modeling and simulation in the communication and signal processing domains. Behavioral representations of practical wireless communication systems typically...
The design of complex analog front-ends demands the exploration of a huge design space at different levels of abstraction and using a multitude of simulators. One of the main issues is to guarantee the consistency of the models and the model parameters between the different abstraction levels. A methodology and a tool, called NETLISP, has been developed for the purpose of guaranteeing the consistency...
Multimedia applications usually have throughput constraints. An implementation must meet these constraints, while it minimizes resource usage and energy consumption. The compute intensive kernels of these applications are often specified as synchronous dataflow graphs. Communication between nodes in these graphs requires storage space which influences throughput. We present exact techniques to chart...
We present a 4-bit power scalable flash analog-to-digital converter in digital 0.18-mum CMOS, targeting low power ultra-wide band receivers. To minimize static power consumption, we exploit dynamic comparators with built-in digitally tunable thresholds. The converter has been realized and tested outperforming recent comparable designs even in more advanced technologies. The main performance figures...
This paper presents a heterogeneous specification methodology built on top of the standard SystemC kernel. The methodology enables abstract specification supporting heterogeneity, which in this context entails the ability to describe and connect parts of the system specification under different models of computation (MoCs). A main and distinguishing contribution of the methodology is that the support...
In this paper we present SOC-NLNA, a systematic synthesis methodology for fully integrated narrow-band CMOS low noise amplifiers (LNA) in high performance system-on-chip (SoC) designs. SOC-NLNA is based on deterministic numerical nonlinear optimization and the normal boundary intersection (NBI) method for Pareto optimization. To enable SoC integration, we simultaneously optimize both devices and passive...
Process induced threshold voltage variations bring about fluctuations in circuit delay that affect the FPGA timing yield. We propose an adaptive FPGA architecture that compensates for these fluctuations. The architecture includes an additional characterizer circuit that classifies logic and routing blocks on each die according to their performance. Base on this classification, the architecture adaptively...
This paper presents analysis methods for energy estimation in RC trees driven by time-varying voltage sources, e.g., buffers, time-varying power supplies, and resonant clock generators. An Elmore energy model that is the computational analog of the conventional Elmore delay model for RC trees is described. Simulation results indicate that the error in energy estimation is less than 2.5% in the worst-case...
In this paper, we propose a novel technique on mining relationships in a sequential circuit to discover global constraints. In contrast to the traditional learning methods, our mining algorithm can find important relationships among several nodes efficiently. The nodes involved may often span several time-frames, thus improving the deducibility of the problem instance. Experimental results demonstrate...
This panel discusses the following topics. With the ongoing trend towards more and more digitization in applications ranging from multimedia to telecommunications, there is a big debate about whether there will remain a need for analog circuits in scaled technologies. Analog circuits do not seem to take advantage of nanometer CMOS; rather they suffer from it. So if the question is asked "will...
In this paper, we propose a test pattern ordering algorithm for fault diagnosis. Test pattern ordering is effective in situations where the fail log is truncated and contains a limited number of fail data. In such cases, higher diagnostic resolution can be achieved with the test set appropriately ordered. Test pattern ordering is independent of the diagnosis algorithm used. The higher resolution achieved...
Communication latency and power consumption are two competing objectives in network-on-chip (NoC) design. This paper proposes a novel method that unifies these two objectives in a multi-commodity flow (MCF) formulation. With an improved fully polynomial approximation algorithm, power efficient design of an 8 times 8 NoC can be found for given average latency constraints with certain communication...
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