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This paper describes the design and implementation of an FPGA-based transverse multibuch feedback system for Diamond Light Source. The system is designed to damp instabilities of the electron beam up to 250~MHz in both horizontal and vertical planes. The feedback algorithm and diagnostics features are implemented and verified using SystemVerilog HDL language on a Xilinx XCV2P30 FPGA.
This paper presents three different control techniques to couple a Coarse-Grain Reconfigurable Architecture (CGRA) with a generic RISC processor. In the architecture under study the CGRA, i.e., a coarse-grain array, works as co-processor and is used to accelerate a kernel selected by the application developer. The array is meant to perform the data processing operations of the kernel, while the RISC...
A Network Intrusion Detection System (NIDS) inspects the traffic flowing in a network to detect malicious content such as spam, viruses, and so on. Hardware based solutions appear necessary to face the performance requirements emerging when the goal is to deploy such systems in high speed network scenarios. However, the appropriate choice of the hardware platform is believed to be subject to at least...
Computer architectures for advanced driver assistance systems have become increasingly important in the automotive industry. They target safety-critical applications, which process large amounts of incoming sensor data. This is especially the case for image processing applications, which must handle several uncompressed image streams from multiple cameras. As one possible target architecture, FPGAs...
A new method to synthesize clusters of floating-point addition operations on FPGAs is presented. Similar to Altera's floating-point data path compiler, it performs normalization once, at the output of the cluster operation. All significands in the clustered operation are denormalized in parallel with respect to the largest exponent: a fixed-point compressor tree then sums the aligned significands,...
This paper introduces a flexible, hybrid emulation platform for processor related emulation. It is based on a modern Xeon server and FPGA. With Intel processors implemented in FPGA and plugged into the Xeon server's processor socket, and with the Xeon BIOS modified to accommodate different cores, this platform is able to boot OS and run applications while interacting with the Xeon server's native...
Simulated annealing has became the de facto standard for FPGA placement engines since it provides high quality solutions and is robust under a wide range of objective functions. However, this method will soon become prohibitive due to its sequential nature and since the performance of single-core processor has stagnated. General purpose computing on graphics processing units (GPGPU) offers a promising...
Parameterizable configurations are regular FPGA configurations in which some of the configuration bits are expressed as Boolean functions of a set of parameters. These configurations can be rapidly transformed to a specialized configuration by evaluating the Boolean functions for a specific set of parameter values and are therefore ideal for use in run-time reconfigurable systems. To accommodate the...
Regular expression pattern matching circuits have been implemented based on NFA. Most of them adapted the one-hot state encoding. Recently FPGAs with 6-input lookup tables (6-LUTs) such as Virtex-5 has been announced. However, if regular expression matching circuits are implemented using one-hot encoding on FPGAs with 6-LUTs, additional inputs of 6-LUTs may be wasteful. In this paper, we propose a...
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