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Effective reconfigurable hardware (RH) allocation plays a critical role in multi-tasking systems. Past RH scheduling research has focused on how to allocate RH based on the area and performance of competing hardware kernels. However, these approaches generally assume that the metrics associated with those hardware kernels are pre-determined. However, design-time estimates may not always be accurate...
A dynamically self-reconfigurable master-slaves MPSoC architecture framework is introduced which can be fully embedded into a single FPGA device. The master core can request a configuration manager module to add, or remove, a slave core at runtime. If the request can be satisfied, self-reconfiguration commences, implemented by a pipeline of light-weight specialized blocks. The M-S architecture utilizes...
The increased use of multi-bit processing elements such as digital signal processors, multipliers, multi-bit addressable memory cells, and CPU cores has presented new opportunities for Field-Programmable Gate Array (FPGA) architects to utilize the regularity of multi-bit signals to increase the area efficiency of FPGAs. In particular, configuration memory sharing has been traditionally used to exploit...
This paper presents a non-monolithic top-down reconfigurable multiplier suitable for embedding in an FPGA structure. It is constructed of four individual partitions that can operate as separate multipliers but also concatenate to form a superior multiplier with increased precision and sign handling ability. The number of possible operation modes is limited in order to keep the reconfiguration overhead...
Many reconfigurable hardware architectures have been proposed so far, ranging from FPGAs to coarse grained architectures. Reconfigurability can be intended in several ways, and a number of diverse solutions have been proposed. One of the most relevant issues that have emerged is that the performance gain offered by reconfigurable hardware is balanced by relevant difficulties in their programming,...
In this paper a method for symbolic decomposition of functions with multi-valued inputs and outputs is presented. Decomposition is performed simultaneously with an encoding of symbolic values. In this way an impact of input/output encoding on decomposition efficiency is taken into consideration during optimization. The input/output encoding is built in the balanced decomposition strategy based on...
Over the last years LDPC codes became more and more popular because of their near Shannon limit error correcting performance. Structured code classes which ease decoder design have already been standardized for DVB-S2, IEEE WiMax 802.16e or WiFi. In this paper we introduce a flexible decoder architecture which can decode any structured or unstructured LDPC code using the identical hardware. Furthermore...
A geometric programming framework is proposed in this paper to automate exploration of the design space consisting of data reuse (buffering) exploitation and loop-level parallelization, in the context of FPGA-targeted hardware compilation. We expose the dependence between data reuse and data-level parallelization and explore both problems under the on-chip memory constraint for performance-optimal...
This paper describes CHiMPS, a C-based accelerator compiler for hybrid CPU-FPGA computing platforms. CHiMPSpsilas goal is to facilitate FPGA programming for high-performance computing developers. It inputs generic ANSIC code and automatically generates VHDL blocks for an FPGA. The accelerator architecture is customized with multiple caches that are tuned to the application. Speedups of 2.8x to 36...
Due to continuous improvements in the resources available on FPGAs, it is becoming increasingly possible to accelerate floating point algorithms. The solution of a system of linear equations forms the basis of many problems in engineering and science, but its calculation is highly time consuming. The minimum residual algorithm (MINRES) is one method to solve this problem, and is highly effective provided...
We present here a novel approach to use FPGA to accelerate the Haar-classifier based face detection algorithm. With highly pipelined microarchitecture and utilizing abundant parallel arithmetic units in the FPGA, wepsilave achieved real-time performance of face detection having very high detection rate and low false positives. Moreover, our approach is flexible toward the resources available on the...
Traditional design of network processors is complicated by two conflicting demands, flexibility and performance. On the one side, network processors should be flexible enough to adapt to changing protocols and varying traffic profiles, on the other side they have to cope with increasing data rates of network links. This demonstrator shows that runtime reconfigurable systems have the potential to optimise...
In this paper, we introduce a constraint programming-based approach for the optimization of area and of reconfiguration time for communication networks for a class of regular 2D reconfigurable processor array architectures. For a given set of different algorithms the execution of which is supposed to be switched upon request at run-time, we provide static solutions for the optimal routing of data...
Support vector machines (SVMs) are an effective, adaptable and widely used method for supervised classification. However, training an SVM classifier on large-scale problems is proven to be a very time-consuming task for software implementations. This paper presents a scalable high-performance FPGA architecture of Gilbertpsilas Algorithm on SVM, which maximally utilizes the features of an FPGA device...
The following topics are dealt with: field programmable gate arrays; encryption; network-on-chip; image processing; video processing; ASICs; reconfigurable architecture compiler; reconfigurable processors; random number generators; PLL; hardware-software codesign; financial modelling; biological modelling and algorithm acceleration.
Recent improvements in the memory capacity of Field Programmable Gate Arrays (FPGAs) have spurred interest in using the devices for arithmetic floating-point operations. However, adapting a program designed to run on a sequential processor to be run instead on an FPGA can be time-consuming and difficult for anyone lacking significant experience in hardware design. In this paper we use a high-level...
As the use of FPGAs increases, the importance of highly optimized processors for FPGAs will increase. In this paper we present the microarchitecture of a soft microprocessor core optimized for the Virtex-4 architecture. The core can operate at 357 MHz, which is significantly faster than Xilinxpsila Microblaze architecture on the same FPGA. At this frequency it is necessary to keep the logic complexity...
In the last years, aside from fine-grained reconfigurable architectures such as FPGAs, coarse-grained reconfigurable architectures (CGRAs), which typically have building blocks of a fixed bit-width (8 bit, 16 bit, etc.), have gained in importance in academia as well as in industry. CGRAs are usually used for domain-specific computations and have advantages over traditional FPGAs in terms of area and...
In the context of FPGAs, system downgrade consists in preventing the update of the hardware configuration or in replaying an old bitstream. The objective can be to preclude a system designer from fixing security vulnerabilities in a design. Such an attack can be performed over a network when the FPGA-based system is remotely updated or on the bus between the configuration memory and the FPGA chip...
We propose a new method for defragmenting the module layout of a reconfigurable device, enabled by a novel approach for dealing with communication needs between relocated modules and with inhomogeneities found in commonly used FPGAs. Our method is based on dynamic relocation of module positions during runtime, with only very little reconfiguration overhead; the objective is to maximize the length...
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