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Mask programmable gate arrays (MPGAs) are an attractive solution to reduce design cost and turnaround time in ultra-deep submicron technologies. Several design methodologies have been proposed in the recent years for converting an evaluated field-programmable gate-array (FPGA) prototype design into an MPGA. In this paper, we investigate a predefined regular routing architecture of an MPGA. The routing...
Recent developments in process technology have made it possible to produce chips consisting of a large number of processing elements. For factors such as scalability, performance, power-efficiency, the interconnection structure supporting such a chip needs to be an on-chip network architecture rather than a conventional bus-based system. Recent research has studied such network-on-chip (NoC) based...
Research in the fields of physics, chemistry and electronics has demonstrated that quantum-dot cellular automata (QCA) is a viable alternative for nano-scale computing. However, little work on QCA has studied designing implementation-friendly programmable QCA circuits. This paper fills this gap by presenting a novel QCA-based programmable logic array (PLA) structure. In addition to being compact,...
It is shown that sub-0.1 mum Si nanocrystal bulk MOSFET with thin SiN tunnel insulator is a very strong random noise source used in high-rate small-size random number generation circuit, which is required for cryptograph application in mobile network security. A fast random number generation rate of 0.12 MHz is demonstrated using Si nanocrystal MOSFET and a simple small circuit. It is suggested that...
This paper presents an on-chip network for a runtime reconfigurable system-on-chip. The network uses packet-switching with virtual channels. It can provide guaranteed services as well as best effort services. The guaranteed services are based on virtual channel allocation, in contrast to other on-chip networks where guarantees are provided by time-division multiplexing. The network is particularly...
In recent years, integrating high-level synthesis and physical design has become essential for successful timing closure. In this paper, we present a novel probabilistic approach to perform integrated datapath allocation and floorplanning. In contrast to existing methodologies that tradeoff high-level design space searched with accuracy of physical estimates, the proposed methodology performs exhaustive...
On-chip buses in deep sub-micron designs consume significant amounts of power and have large propagation delays. Thus, minimizing power consumption and propagation delay are the most important design objectives. In this paper, we propose a technique for delay and energy efficient data transmission for on-chip buses and evaluate the effectiveness of our technique by focusing on the LI cache address/data...
Hash functions play an important role in modern cryptography. This paper investigates optimisation techniques that have recently been proposed in the literature. A new VLSI architecture for the SHA-256 and SHA-512 hash functions is presented, which combines two popular hardware optimisation techniques, namely pipelining and unrolling. The SHA processors are developed for implementation on FPGAs, thereby...
Increasing use of scratch-pad memories (SPMs) in embedded systems makes it imperative to consider optimizations tailored to their needs. Since these memories are managed by software, they present unique opportunities to the designer/compiler writer as far as energy optimizations are concerned. This paper proposes and quantifies the benefits of a compiler-directed energy optimization scheme for banked...
This paper investigates the performance and power dissipation of globally asynchronous locally synchronous (GALS) multi-processor systems. We show that communication loops are a source of significant throughput degradation in communications links and that there is no degradation whatsoever under certain conditions for one-way links, and that it is possible to design GALS multiprocessors without this...
Sparse tree adders are a common choice for the implementation of high performance binary addition. However, for constant supply voltage they have constant energy consumption regardless of the operating frequency. This paper presents a dual-mode sparse tree adder that offers a low-speed low-energy mode. This is achieved by disabling the prefix tree in the low-speed mode. Simulation results using extracted...
Buffer insertion plays an increasingly critical role on circuit performance and signal integrity, especially in deep submicron region. Buffer insertion stage is very important for buffering efficiency. Early buffer insertion (e.g. at the floorplanning stage) may cause misestimation due to unknown cell locations, on the other hand buffer insertion after placement or during global routing may tend to...
This paper presents a novel technique for simulation of dynamically and partially reconfigurable systems using SystemC. Its kernel was modified in order to enable the deactivation of any module at simulation time. An example of how to use this technique is presented. Simulations using our MPEG-4 decoder implementation are being developed
Thermal management is becoming increasingly important in circuit designs with high power density. Circuits that overheat beyond specified operating conditions may suffer timing failures, or become damaged for various reasons, including thermal runaway. We present a novel application of a thermally sensitive circuit to automatically regulate the performance and power consumption of asynchronous circuits,...
Dynamic and partial reconfiguration of FPGAs enables systems to adapt to changing demands. This paper concentrates on how to take into account specificities of partially reconfigurable components during the high level adequation algorithm architecture process. We present a method generates automatically the design for both partially and fixed parts of FPGAs
The effect of components' region-constrained placement on reducing internal nets total capacitance and the corresponding change in internal nets' total dynamic power consumption is investigated. Two logic circuits were specified as components covering around 80% of total FPGA busy gates. These components are multiplexers and adders along with multipliers. Each of these components was implemented on...
Short time-to-market pressure, high cost and risks and power consumption are keywords in development of microelectronic solutions for embedded systems as well as for universal and application tailored processor architectures. Modularity and flexibility while design-time, e.g. for system-on-chip (SoC) component design, is not sufficient if the possibility of run-time reconfiguration of novel architectures...
In this paper the design and implementation of a unique service-time-stamp computation circuit, called the finishing tag, for WFQ based packet scheduling is presented. The implementation is based on UMC 130nm standard cell technology, and placed and routed using Cadence SoC encounter. The design targets the development of programmable IP packet scheduling circuits for next generation network processing...
This paper proposes an adaptable receiver architecture for the WCDMA downlink UMTS standard. The architecture is aimed to support the receiver in such a way that it can self-adapt to different channel conditions. Architectural optimizations aiming to a more efficient implementation are presented and the advantages of the self-adaptable behavior of the receiver under a Rayleigh channel are shown
In this paper, we propose a new design methodology for clockless circuits based on the present methodology of clocked circuits. This methodology takes advantage of the maturity of current CAD tools to synthesize new clockless pipelines without disrupting their design flow. Currently, there is no established design methodology to support the design and verification of clockless circuits. As a case...
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