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Cognitive computing is capable of machine learning, recognition and proposal. It has a great potential to make human life richer, more productive and more intelligent. For the realization of the cognitive computing, an efficient and scalable non-von Neumann architecture inspired by the human brain structure has been developed and a device which demonstrates the concept was also built. This device...
This paper provides a comparison of bonding process technologies for chip and wafer level 3D integration (3Di). We discuss bonding methods and comparison of the reflow furnace, thermo-compression, Cavity ALignment Method (CALM) for chip level bonding, and oxide bonding for 300 mm wafer level 3Di. For chip 3Di, challenges related to maintaining thin die and laminate co-planarity were overcome. Stacking...
Optical out coupling is one of the key research items of silicon photonic packaging. It is necessary to realize robust, high-bandwidth, low-power optical data communication system in an economical way. Because material interfaces are always involved for the coupling, the reflection loss at the interface often occupies a major part of loss. Here we report on an ideal anti-reflection coating method...
Fine precision is necessary in assembling silicon photonics devices, because of single mode optical signals and smaller waveguides on silicon due to the high refractive index of silicon. It is necessary to lower the loss in the optical path for low power and stable operation of optical transceivers,. We report on several new approaches to solve the precision requirement and low loss requirement by...
We have studied a thermo-compression bonding method for high density interconnections. Fluxes are commonly used in conventional solder bonding. However, flux applications have several issues such as the void generation in solder and the flux residue remaining between bumps. These could degrade their reliabilities seriously when the bump pitch becomes small since these features do not scale to bump-pitch...
3D organic packages with three-die stack were evaluated by finite element analyses and thermal cycle tests. The thermal cycle tests with different silicon thickness configurations were performed. The die-stack test vehicles with thin top die (150μm) did not show any failures during the 2000 cycles of thermal cycle tests. However, failures were detected for the test vehicles with thick top dies (400μm)...
In ASET (Association of Super Advanced Electronics Technologies), the thermal resistances of three-dimensional (3D) chip stacks have been measured by using 3D stacked thermal test chips which are implemented with PN junction diodes for temperature sensors and diffused resistors for heating. The equivalent thermal conductivity of interconnection between stacked chips (SnAg + Cu post) and that of TSV...
The thermal resistance of a three-dimensional (3D) chip stack is evaluated, based on the measured thermal resistances of 3D stacked thermal test chips which are implemented with PN junction diodes for temperature sensors and diffused resistors for heating. It is discussed how much heat generation of a 3D chip stack is permitted, when a conventional cooling from the top of a 3D chip stack is assumed...
The exascale computing is required in the Era of Big Data. In order to achieve this demand, new technology innovation must be required and packaging scaling including 3D-IC with TSV (Through Silicon Vias) is one of most promising technology. To increase the total bandwidth, the fine pitch die to die interconnection is necessary. Micro-bumping, thermally enhanced underfill and advanced interposer technologies...
Packaging of 3D die stacks on organic laminates is a low-cost approach to achieve devices with high density I/O and short wiring delays. However, the large mismatch in coefficients of thermal expansion between components in the package causes deformation and high stress in the constituting elements. The components such as thin dies, metal through silicon vias, fine-pitch interconnections are susceptible...
For the thermal management of three-dimensional (3D) chip stack, its thermal resistance needs to be clearly understood. In this study, 3D stacked test chips are fabricated, which are implemented with PN junction diodes for temperature sensors and diffused resistors for heating. At SemiTherm2011, the equivalent thermal conductivity of the interconnection, including BEOL (Back-End-Of-the-Line, wiring...
The thermo-mechanical reliability of stacked die structures is a critical issue in 3D packaging. The assessment of the stress and the warpage of silicon dies in 3D stacked structures become important in achieving low-stress and low-warpage 3D packaging. However the parametric analyses of thermal stress and die-warpage by rigorous finite element analysis can be time consuming for 3D systems, since...
TSV (Through Silicon Via) is one of the key elements for building 3D integrated silicon devices with high bandwidth interconnections. In this paper, we propose a diagnostic method for TSV defects by using X-ray projection microscopy. By optimizing the image contrast of the X-ray projection micrographs in reference to its X-ray intensity histogram, we could obtain the small defect features in TSVs...
To propose an appropriate cooling solution for a three-dimensional (3D) chip stack at the design phase, it is necessary to estimate the total thermal resistance of a 3D chip stack. The interconnection between stacked chips is considered as one of the thermal resistance bottleneck of a 3D chip stack, but it is not experimentally clear yet. We have previously measured the thermal conductivity of SnAg...
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