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Fine pitch interconnect is one of key technology elements for 2.5D and 3D IC. Low cost and flexibility in technical aspects are also important, so that the technology can be used for wide range of applications. We have newly developed a non-strip type photosensitive resin and propose a novel IMS bumping process with it for finer pitch flip chip joining in a further cost-effective way. The photosensitive...
Injection Molded Solder (IMS) is an advanced solder bumping technology that the solder bumps can be made by injected pure molten solder through the masks. In this study, we investigated effects of solder wettability of resist mask on solder filling performance by solder flow simulation with computational fluid dynamics (CFD) software and experiments with IMS technology. It was confirmed by the simulation...
When a 3D chip stack is composed of some memories and a logic device such as processor, the logic device has been assumed to be located as a bottom chip in wide I/O and HBM applications. On the other hand, for high-end server applications, a processor needs to be located as a top chip because it needs to be cooled efficiently. In this case, many Through Silicon Vias (TSVs) are necessary in a memory...
Cognitive computing is capable of machine learning, recognition and proposal. It has a great potential to make human life richer, more productive and more intelligent. For the realization of the cognitive computing, an efficient and scalable non-von Neumann architecture inspired by the human brain structure has been developed and a device which demonstrates the concept was also built. This device...
Novel bumping technology that can realize high density assembly of IC chips and packages with a high number of I/O is required in the field of electronic packaging. Currently, the electroplating method or the solder ball placement method have been widely adopted for the fabrication of solder bumps down to sub-hundred microns in diameter. However, there are some limitations with these current bumping...
The thermal resistance of a three-dimensional (3D) chip stack has been experimentally clarified by authors [1–6] and an additional cooling solution is strongly required to achieve various structures of 3D chip stacks. Especially, when a high heat dissipating chip is located as a bottom chip, cooling from the bottom side of chips (in other words, from the laminate (substrate) side) is identified to...
In conventional SiP (System in Package), several semiconductor chips had been 2D arranged in an interposer and a mother board. However, it is difficult to downsize and improve the performance of electronic devices due to that large area is occupied by the chips. Recently, 3D packaging technology has been investigated to reduce size of devices and to improve performance of semiconductor devices [1-11]...
Recently, the downsizing and high-performing semiconductor packages have been developed and 3D packaging has been spurred research into reliability of TSV (through silicon via) [l]-[9]. In conventional SiP (System in Package), several semiconductor chips had been arranged in a plate. It is difficult to correspond to downsizing and high-performing of electronic devices because that large area is occupied...
For the thermal management of a three-dimensional (3D) chip stack, cooling from the bottom side of chips (in other words, from the laminate (substrate) side of chips), in addition to conventional cooling from the top surface of chips, is proposed. For cooling from the bottom side of chips, it is essential to consider the trade off among thermal, electrical and mechanical performance. Firstly, the...
In this paper, we will describe a new low cost solder bumping technology for use on wafers. The wafer IMS (injection molded solder) process can form fine pitch solder bumps on wafers, while offering greater solder alloy flexibility. This method is also applicable to form uniform solder bump heights when a wafer has different size and shape of I/O pads. The wafer IMS bumping process uses a solder injection...
Organic interposer which utilize existing manufacturing infrastructure and material, has capability and potential to be in low cost. Furthermore, organic material property which has lower relative dielectric constant (Dk) than silicon dioxide (SiO2) potentially realizes higher bandwidth, keeping particular characteristic impedance on transmission line. In this paper, we focus on a simple chip-to-chip...
Thermal stresses around void in TSV (Through Silicon Via) structure in 3D SiP were discussed under the conditions of device operation and reflow process by using FEM (Finite Element Method). In case of the condition of device operation, equivalent stress around void inside Cu TSV was estimated at around 100 MPa. It showed the low possibility for low cycle fatigue of Cu TSV under device operation because...
Injection Molded Solder (IMS) is an advanced solder bumping technology that the solder bumps can be made by injected pure molten solder through the masks. In this study, 3 different sizes of bumps were fabricated by IMS with PI film mask. 3 different solder types, Sn-Ag-Cu, Sn-Bi, and In-Sn were selected for this study. Firstly, effects of IMS stage temperature on bump mechanical integrity for Sn-Ag-Cu...
The stresses of TSV (Through Silicon Via) and Si chips in 3D-SiP were discussed with a large scale simulator based on FEM (Finite Element Method), ADVENTURECluster. In this study, the stacked layer structure of Si chips is modeled accurately. Thermal stress simulation for TSV structure in Si chips is carried out under thermal loads due to device operation and reflow process. In case of device operation,...
We have studied a thermo-compression bonding method for high density interconnections. Fluxes are commonly used in conventional solder bonding. However, flux applications have several issues such as the void generation in solder and the flux residue remaining between bumps. These could degrade their reliabilities seriously when the bump pitch becomes small since these features do not scale to bump-pitch...
It has been experimentally clarified that one of the thermal resistance bottlenecks of a three-dimensional (3D) chip stack is interconnection (solder bumps and underfill) between stacked chips. High thermal conductivity underfill, which we call high thermal conductivity inter chip fill (ICF), is expected to reduce the thermal resistance of interconnection efficiently, because the area which is occupied...
Silicon and glass interposers provide a solution to keep scaling of C4 dimensions and chip-to-chip interconnect density by supporting high bandwidth. However there are still some challenges in the fabrication process and cost. As another alternative solution, organic material would be a candidate. In order to perform the feasibility study for allowable bandwidth with organic material, various electrical...
3D organic packages with three-die stack were evaluated by finite element analyses and thermal cycle tests. The thermal cycle tests with different silicon thickness configurations were performed. The die-stack test vehicles with thin top die (150μm) did not show any failures during the 2000 cycles of thermal cycle tests. However, failures were detected for the test vehicles with thick top dies (400μm)...
In ASET (Association of Super Advanced Electronics Technologies), the thermal resistances of three-dimensional (3D) chip stacks have been measured by using 3D stacked thermal test chips which are implemented with PN junction diodes for temperature sensors and diffused resistors for heating. The equivalent thermal conductivity of interconnection between stacked chips (SnAg + Cu post) and that of TSV...
One of the biggest challenges for future high-performance three dimensional (3D) integrated devices is heat removal from the stacked dies. In this study, thermally enhanced pre-applied type underfills were studied. These materials were formulated considering fillet cracks and delaminations that appeared in thermal cycling tests on 2D organic package. Finally, the applicability for 3D integration processing...
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