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This paper applies for the first time an RF equivalent of the four-point probe Kelvin DC technique to characterize the TSV inductance. This RF approach is based on two-port S-parameter measurements over a wide frequency range using a vector network analyzer (VNA). The approach is easy to implement to determine the TSV inductance, which can be complementary to the DC Kelvin measurements. In addition,...
In this work we present a novel technique to fabricate embedded 3D MIM capacitor on Si interposer showing capacitance densities as high as 96 nF/mm2 and low leakage current of 1.5 pA/nF, while having a breakdown voltage of 10.5 V and > 10 years lifetime (T50%@1V, 100 ˚C = 5.18e16 s).
High speed TSV signals can penetrate through the dielectric liner material, transfer in the silicon substrate and degrade the performance of FEOL devices. In this paper we investigate TSV noise coupling to active device including both FinFET and planar transistors. Calibrated TCAD models are used to perform time domain analysis and understand the mechanisms of substrate noise interaction with active...
Adding functionality to a passive Si interposer used in 2.5/3D integration, can result in system cost reductions. In this work, active components (diodes, BJT, …) have been integrated on Si interposer using a new low-mask process flow. This low-cost process enables: (1) to move part of the area hungry ESD protection from the stacked dies to the interposer; (2) the realization of pre-bond testable...
Adding functionality to a passive Si interposer used in 2.5/3D integration, can result in system cost reductions. In this work, active components (diodes, BJT, …) have been integrated on Si interposer using a new low-mask process flow. This low-cost process enables: (1) to move part of the area hungry ESD protection from the stacked dies to the interposer; (2) the realization of pre-bond testable...
Through Silicon vias (TSVs) are a key breakthrough in 3D technology to shorten global interconnects and enable the heterogeneous integration. However, TSVs also introduce an important source of noise coupling arising from electrical coupling between TSVs and the active devices. This paper investigates the TSV noise coupling to active devices including both FinFETs and planar transistors based on two-port...
Evaluating the importance of electromagnetic (EM) coupling from through silicon vias (TSVs) has become crucial to the design of three-dimensional integrated circuits (3D-ICs). One of the most important parasitic contributions to signal propagation in 3D-ICs is the TSV capacitance. It is both frequency and bias dependent since a TSV is a metal-oxide-semiconductor (MOS) structure. In this work, anomalous...
This paper explores the possibility to use insulating spin-on dielectric materials for 2.5D interposers. Up to 7 photosensitive materials have been investigated in terms of minimum line/space and via resolution to determine the maximum wiring density. In addition the electrical performances of the best materials were assessed in DC and RF to extract the dielectric constant and loss tangent. Finally...
A test system for memory-logic communications in silicon interposer is introduced as well as a performance analysis methodology including a fitted model based on eye diagram measurements. First results of the test system with 9 and 18 mm-long interconnects and a 5 channel bus of micro-strip lines with 2-2 and 5-5 μm width and spacing (W-S), targeting Wide-IO communication standard are presented. Measured...
RF losses and non-linear behavior of RF passive elements such as coplanar transmission lines and inductors are analyzed. The investigated trap-rich HR-Si wafers with a fixed oxide layer of 150 nm-thick show true effective resistivity values higher than 4 kΩ-cm up to 5 GHz and harmonic distortion levels lower than −90 dBm for a 900 MHz input with signal level of +25 dBm. High quality factor of 60 is...
Thick porous Si layers locally formed on a low resistivity Si wafer were studied for their application in on-chip RF device integration. A comparison was made between the above porous Si substrate and trap-rich high resistivity Si (trap-rich HR Si), which constitutes a state-of-the-art substrate for RF integration, by integrating identical co-planar waveguide transmission liness (CPW TLines) on both...
We present for the first time the RF and linear performance of commercial 200 mm trap-rich HR-SOI wafers. These wafers are fully compatible with the thermal budget of CMOS process. The investigated SOI wafers with a fixed BOX of 400 nm-thick show effective resistivity values higher than 4 kΩ-cm and harmonic distortion levels lower than −81 dBm for a 900 MHz input signal with +15 dBm, i.e. more than...
As CMOS technology continues to scale down, allowing operation in the GHz range, it provides the opportunity of low cost integration of analog, digital and RF functions on the same wafer for System-on-Chip (SoC) applications [1]. SoC circuits on Si are prone to substrate losses and coupling, especially when RF analog and digital functions are integrated together into the same chip. In digital circuits,...
This work investigates the influence of high-energy neutrons on oxidized high-resistivity Si substrates. Two oxide thicknesses as well as the presence of a trap-rich passivation layer are considered. The impact of neutron irradiation is directly related to the competition between the generation of interface traps, which are beneficial to reduce parasitic surface conduction (PCS) into the Si substrate...
During 2006 and spring 2007, integration and commissioning of trigger and data acquisition (TDAQ) equipment in the ATLAS experimental area has progressed. Much of the work has focused on a final prototype setup consisting of around eighty computers representing a subset of the full TDAQ system. There have been a series of technical runs using this setup. Various tests have been run including ones...
ATLAS is one of the four experiments under construction along the Large Hadron Collider (LHC) ring at CERN. The LHC will produce interactions at a center-of-mass energy equal to radics = 14 TeV at 40 MHz rate. The detector consists of more than 140 million electronic channels. The challenging experimental environment and the extreme detector complexity impose the necessity of a common scalable distributed...
ATLAS is one of the four experiments under construction along the Large Hadron Collider at CERN. During the 2004 combined test beam, the GNAM monitoring system and the OHP histogram presenter were widely used to assess both the hardware setup and the data quality. GNAM is a modular framework where detector specific code can be easily plugged in to obtain online low-level monitoring applications. It...
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