The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Designing an advanced, miniaturized and reliable system utilizing RFIC and MMICs technologies and packaging design are reaching an inflection point where simulation results from multiple CAD tools are to be cobbled together to predict the performance. Operating at higher frequencies, shrinking the system size, tightly integrating more functionality on chips and dense packaging schemes trigger more...
Packaging of 2.5D/3D applications is disrupting the high-density advanced package (HDAP) segment as silicon and packaging processes converge to deliver fan-out wafer level (FOWLP) and interposer based solutions. Silicon foundries are now in the package supply chain and driving methodology changes that impact manufacturing data formats, and how that data is accepted and verified.
After many years of packaging evolution as main industrial driver for 3D integration, even denser integration scheme have gained recently more interest. Slowdown of Moore's law while maintaining the need of high performance and/or low power from one hand, and a combination of performance / form factor from the other, lead research to innovation and alternative solutions.
Heterogeneous integration delivers “the best junction for the function” to achieve the highest performance by utilizing a known good die strategy. However as technology emerges with more complex systems, die-package co-design becomes a mandatory aspect in the design phase to mitigate risk and foresee results before the entire system is built. Various aspects of such design is reviewed in this work...
A front-illuminated global-shutter CMOS image sensor has been developed with super 35-mm optical format. We have developed a chip-on-chip integration process to realize a front-illuminated image sensor stacked with 2 diced logic chips through 38K micro bump interconnections. The global-shutter pixel achieves a parasitic light sensitivity of −99.6dB. The stacked device allows highly parallel column...
In this work, a 3-D IC architecture is proposed that composes an odd tier-number to provide enough flexibility to a circuit block at a specific tier to connect blocks at all other tiers. For a three-tier structure, it provides flexibility to a circuit block at the bottom or top layer in order to simultaneously connect blocks assigned to other layers. Such architecture would result in lower thermal...
We demonstrate a front-side process integration method to insert high-density 1.2um diameter Tungsten (W) Through Silicon Vias (TSVs) into advanced-node logic wafers after metal-4. This late-TSV-middle approach offers the ability to build 3D technology into commercially available 90nm-node CMOS, while avoiding many of the challenges associated with TSV-last integrations. We also demonstrate a TSV-reveal...
This paper presents a part of a cellular transmitter chain implemented in a 28 nm CMOS 3D integrated circuit vertical stack. The design examines various partitioning topolgies between the analog and digital blocks. By using extensive reconfigurability we are able to create a basis for comparison between the partitions as well as between other partitioning solutions as multiple chip, single chip and...
A breakthrough in vertical stacking and bonding method in flexible substrates is developed and presented in this paper. Unlike current ACF and NCP approaches, which are used in most manufacturing industry, our novel stacking method uses only metal thin film as bonding material. Two different bonding material bumps are carried out in our experiment. Both show better electrical and reliability outcomes...
This paper presents experimental results for a prototype pixel detector with 3.0-μmφ gold cone bumps fabricated by NpD (nanoparticle deposition) and Stacked CdTe/Si X-ray sensor TEG with gold cylindrical bumps fabricated by a low-incident-angle deposition method. The both bump resistances are less than 0.5ohm.
In this paper, heat transfer in 3D IC system is investigated using practical and novel materials for Inter Layer Dielectric (ILD) and Thermal Through Silicon Vias (TTSV). The currently used SiO2 ILD is amiss for heat mitigation due to its poor thermal conductivity. The unique thermal and electrical properties of Hexagonal Boron Nitride (h-BN) are explored in this work for improved heat mitigation.
This paper is dedicated to modeling, design, fabrication and characterization of TSV with embedded capacitor, which integrates a TSV and a 3D MIM capacitor into the same trench. An effective capacitance density of 35nF/mm2 has been demonstrated for the embedded capacitor, which closely matches 37nF/mm2 from analytical prediction. It is found that conventional sputtering technology is inadequate for...
The tolerance of device morphology in wafer-level bonding through polymer-coated layer was investigated for the application of 3D integration. Several different pillar heights were fabricated on wafers to simulate the case of bonding with real devices on wafers. Overall, the wafer morphology with polymer-coated layer above devices less than 2 μm can achieve excellent bonding quality. Furthermore,...
The backside via-last through silicon via (TSV) process is a simple and cost-effective approach for three-dimensional integration. However, it has two problems: (1) the notching near the bottom corners of TSVs and (2) the reaction product generated by the etchback step. To overcome these problems and increase TSV yield, we previously proposed a via-last TSV process using notchless Si etching and wet...
Three-dimensional IC (3D IC) is a promising method to enhance IC performance. Conventional 3D ICs consist of vertically stacked several thin IC chips those are electrically connected with lots of through-Si vias (TSVs) and metal microbumps. Metal microbumps are surrounded by organic adhesive. An epoxy-based material, so-called underfill, has been widely used to fill the gap between several chips....
In this work we present a novel technique to fabricate embedded 3D MIM capacitor on Si interposer showing capacitance densities as high as 96 nF/mm2 and low leakage current of 1.5 pA/nF, while having a breakdown voltage of 10.5 V and > 10 years lifetime (T50%@1V, 100 ˚C = 5.18e16 s).
In this paper, we proposed a novel stacked layer of liner structure around the TSV's and verified its performance on noise coupling between them. The performance of proposed structure with different materials and thickness were optimized and verified with respect to the noise coupling reduction. The obtained results show almost equal noise reduction performance of around 40% with the Teflon-Cu-Teflon...
An advanced TSV metallization scheme, featuring a high conformal ALD oxide liner, a thermal ALD WN barrier, an electroless NiB platable seed and a high throughput copper ECD filling is presented. Because of the high conformality of the WN barrier and NiB seed, very thin layers can be deposited, reducing the manufacturing cost significantly, while still guaranteeing continuous barrier/seed layers all...
In this paper, we demonstrate the effect on the heat management by adding both fin to Thermal Through Silicon Vias (TTSV) and heat spreaders to the conventional Three Dimensional Integrated Circuit (3D IC) structure. Various effects such as thermal cooling and its impact on distribution of potential across IC at different conditions have been simulated using COMSOL Multiphysics with various architectures...
Physically meaningful and easy-to-use analytical predictive stress models are developed for a through-silicon-via (TSV) design using theory-of-elasticity based approach. Two extreme cases of the TSV height-to-diameter ratios are considered: disc-like vias, with the aspect ratios below 0.25 (plane stress approximation can be employed in this case), and rod-like-vias, with aspect ratios, above 2.5 (plane...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.