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FinFETs are now widely accepted transistor architecture to replace the two dimensional (2D) metal-oxide-silicon field effect transistors (MOSFETs) into a three dimensional (3D), multi-gate (MG) MOSFETs. The MG FinFETs can be fabricated either on a silicon-on-insulator (SOI) substrate or on a bulk silicon substrate. Both approaches require an advanced patterning not only to improve device performance...
In this paper we include the effect of temperature dependence in our compact model for Double Gate (DG) MOSFETs using advanced transport models, and we show that the model has a good degree of agreement with the 2D numerical simulation obtained using Multisubband Monte Carlo simulation. The core model is based on a compact charge control model for charge quantization. A template device representative...
Short channel junctionless field-effect transistors (JL-FET) were fabricated on a silicon-on-insulator substrate. The channel dimensions were scaled to 20 nm in length and 4 nm in thickness, using anisotropic wet etching of SOI layer. Highly doped channels were formed by diffusion of dopants from the source and drain region at a high temperature annealing. N-type and p-type JL-FETs show drain current...
Nanoelectronics will have to face major challenges in the next decades in order to proceed with increasing progress and drastically reduced to zero variability at the sub 10 nm nodes level. New progress laws combined to the scaling down of CMOS based technology will emerge to enable new paths to Functional Diversification. New materials and disruptive architectures, mixing logic and memories, Heterogeneous...
Statistical variability and reliability is a critical issue in conventional bulk planar MOSFETs of the 20 nm technology. In this paper we present a comprehensive simulation study of the impact of the drain-bias on the statistical variability in corresponding bulk MOSFETs including the threshold-voltage and the drain-induced barrier lowering (DIBL) which are two important transistor figures of merit...
We developed a 2D analytical model for junctionless double gate (DG) MOSFETs valid for all regions of device operation. The 2D solution for the potential enables us to predict electrical parameters, such as threshold voltage and subthreshold slope, as well as current and Ion/Ioff ratios fast and accurate. From the results for the ratios we define an optimum point of device operation for different...
This work presents a well-defined electronic device, namely a n-channel high-k dielectric FinFET (Fin Field Effect Transistor) as new label-free sensor for enhanced sensing integrated circuits. Metal gate FinFETs on bulk Si have been successfully electrically characterized, showing excellent SS (Subthreshold Slope) and high Ion/Ioff ratio. Exposed n-channel FinFETs, integrated on the same die, have...
The usefulness for technology computer-aided design (TCAD) tools of the bulk linear piezoresistive theory is limited for two reasons. The first is that the normal effective field breaks piezoresistive tensor symmetries increasing the number of independent coefficients from three to six. The second reason is due to the non-linear behavior of the mobility change at high stress values. In this paper,...
In this paper the optical optimization of vertical ZnO/CdTe and crystalline silicon/amorphous silicon (c-Si/a-Si) core-shell heterojunction nanowires array solar cells is presented. Optical simulations have been performed by means of a Rigorous Coupled-Wave Analysis (RCWA) numerical simulator which allows the modeling of nanostructured optoelectronic devices with a reasonable trade-off between accuracy...
The two-band k · p Hamiltonian for silicon conduction valleys is able to model the strong non-parabolic bandstructure behavior necessary to reproduce the experimental mobility of (110) nMOSFETs. In this paper we derive analytic results for (110) square wells showing how confinement affects the energy and the effective masses of the electron subbands. Moreover, a numerical implementation coupled to...
Semiconductor spintronics is a rapidly developing field with a potentially large impact on microelectronics. Using electron spin may help to reduce power consumption and increase computational speed of modern electronic circuits. Silicon is perfectly suited for spin-based applications: it is characterized by a weak spin-orbit interaction which should result in a long spin lifetime. However, recent...
The hole-phonon energy loss rate in silicon is measured at phonon temperatures ranging from 300 mK to 700 mK. We demonstrate that it is approximately an order of magnitude higher than the corresponding electron-phonon energy loss rate in the same material over an identical temperature range.
This work explores numerically the short-channel effects in thin-body SOI MOSFETs with shallow source/drain architecture, where the junction depths are less than the associated silicon body thicknesses. Unique fringing field and short-channel behavior are observed in the unconventional SOI devices. Numerical results of the short-channel effects are compared with those in the conventional SOI MOSFETs...
In this paper we use numerical simulations to evaluate the impact of interface roughness scattering on III–V n-type and Ge p-type Implant-Free Quantum-Well (IFQW) MOSFETs suitable for the 10nm CMOS technology generation. We make use of Monte Carlo transport simulations to capture the non-equilibrium effects and evaluate the impact that the spacer between gate and source/drain regions and interface...
Up until recently (i) c-Si and poly-crystalline Si (poly-Si have been assumed to be qualitatively different than (ii) a-Si(H). X-ray absorption and photo-emission studies combined with ab-initio many-electron theory for their interpretation have established that they are indeed much similar. In point of fact, a-Si(H) should be renamed nano-grain (ng)-Si, since some of the more important properties,...
In this paper, the current state of the power electronic device market is reviewed in light of the increased challenge upon Si from the wide bandgap semiconductors SiC and GaN. It is suggested that for the next ten years Si will continue its dominance both at the low voltage, and at the high voltage, high current ends of the market. However, SiC in particular is most likely to make a robust challenge...
Recent achievements of silicon based tunnel field effect transistors (TFETs) and remaining major challenges are overviewed. Particular emphasis is placed on the band to band tunneling (BTBT) junctions, the heart of the device. Dopant segregation from ion implanted ultrathin silicide contacts proved as viable method to achieve steep tunneling junctions. This avoids defect generation by direct implantation...
This paper presents (i) spectroscopic studies of intrinsic vacated O-site defects in non-crystallin(nc-) SiO2, GeO2 and nano-crystalline HfO2 and TiO2, and (ii) proof of concept spectroscopic studies. These indicate electronic structure that favors nc-SiO2 and GeO2 for gate stacks in CMOS devices that push the ultimate limits of thickness scaling reductions, and interfacial engineering. The properties...
An electron cooling junction using platinum silicide as a superconductor contact is demonstrated for the first time. The junction shows encouraging electrical characteristics and a fit to a standard cooling model predicts cooling from 100 mK to 50 mK for a test device. Silicides have been widely used in the semiconductor industry because of their reliability and reduced contact resistance; hence this...
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