Search results for: E. Gnani
chapter
A simulation study on the impact of interface traps (ITs) and strain on the I/V characteristics of co-optimized n- and p-type tunnel field-effect transistors (TFETs) realized on the same InAs/Al0.05Ga0.95Sb technology platform is carried out using a full-quantum simulator. In order to capture the effect of interface/border traps on the device electrostatics in a way consistent with the ballistic approach,...
chapter
2016 IEEE International Electron Devices Meeting (IEDM) > 36.7.1 - 36.7.4
A TCAD-based approach is proposed to investigate the most relevant transport mechanisms of diamond-like carbon (DLC) films at different biases and ambient temperatures. Starting from the band structure and boundary conditions of a metal-insulator-metal (MIM) device, the most relevant trap levels have been determined against experiments along with the Poole-Frenkel conduction effect. The affinity of...
chapter
A new algorithm has been designed and implemented, that allows for the automatic generation of an optimum 2D and 3D grid for device simulation from the information available at the circuit-layout level. The tool fills a gap in the top-down design chain of integrated circuits, easing the task of circuit designers who are often unaware of specific features of device-modeling tools.
chapter
The impact of strain and semiconductor/oxide interface traps (ITs) on the turn-on characteristics of a 10×10 nm2 nanowire (NW) Al0.05Ga0.95Sb/InAs heterojunction n-type tunnel field-effect transistor (TFETs) is carefully investigated using a full-quantum simulator. In order to capture the effect of traps on the device electrostatics in a way consistent with the ballistic approach, the SRH theory has...
chapter
Recent papers on advanced semiconductor devices adopt a model called density-gradient correction, in which the standard electric potential acting on the carriers is modified by a non-linear term involving the carrier concentration and its second derivatives. When applied to cases where quantum effects are not negligible, the modified model improves the results with respect to the standard approach...
chapter
A simulation study exploring the possibility of performance improvements related with the application of stress to nanowire TFETs is carried out. It is demonstrated that appropriate strain conditions, i.e., biaxial tensile strain, induce a remarkable enhancement of the on-state current thanks to bandgap reduction. However, a careful optimization of the device cross-section and strain level must be...
article
Solid State Electronics > 2015 > 113 > Complete > 86-91
A quasi 2D semianalytical model for the potential profile in hetero and homojunction tunnel FETs is developed and compared with full-quantum simulation results. It will be shown that the pure analytical solution perfectly matches results at high VDS. However, a coupling with the numerical solution of the 1D Poisson equation in the radial direction is necessary at low VDS, in order to properly account...
chapter
Today Tunnel FETs are perceived as the most promising small slope transistors, that may enable a significant decrease in the power supply of integrated circuits and thus an improvement of their energy efficiency. However, many experimental results largely differ from the simulations of ideal Tunnel FETs, in fact simulations report small sub-threshold swing (SS) values over several orders of magnitudes...
chapter
In this presentation we shortly discuss the evolution of Microelectronics into Nanoelectronics, according to the predictions of Moore's law, and some of the issues related with this evolution. Next, we address the requirements of device modeling related with an extreme device miniaturization, such as the band splitting into multiple subbands and quasi-ballistic transport. Physical models are summarized...
chapter
In this presentation we shortly discuss the evolution of Microelectronics into Nanoelectronics, according to the predictions of Moore's law, and some of the issues related with this evolution. Next, we address the requirements of device modeling related with an extreme device miniaturization, such as the band splitting into multiple subbands and quasi-ballistic transport. Physical models are summarized...
article
Solid State Electronics > 2015 > 108 > Complete > 104-109
We report for the first time a quantum mechanical simulation study of gate capacitance components in aggressively scaled InAs Nanowire Tunnel Field-Effect Transistors. It will be shown that the gate-drain capacitance exhibits the same functional dependence over the whole Vgs range as the total gate capacitance, albeit with smaller values. However, as opposed to the previous capacitance estimations...
chapter
The electron and hole impact-ionization coefficients in AlxGa1-xN have been calibrated through a Chynoweth law by using a Monte Carlo theoretical study and experimental data at different ambient temperatures. The model has been used to investigate the breakdown characteristics in AlGaN/GaN HEMTs. The concurrent effect of charge trapping in the GaN buffer and impact-ionization generation in the device...
chapter
The sensitivity of HV RESURF LDMOS transistors to parasitic charging in molding compound is investigated in this work by incorporating the passivation and encapsulation layers in the TCAD setup and implementing the conductivity losses in the mold. The role played by field plates and multiple metal/poly-silicon floating rings on the overall RESURF are revisited by focusing on the breakdown voltage...
chapter
A TCAD-based approach has been used to investigate the leakage current and breakdown regime of vertical GaN/AlGaN/Si structures at different ambient temperatures. A good agreement with experimental data has been obtained by implementing both trap-assisted and Poole-Frenkel conduction mechanisms into the buffer layers. The latter mechanisms have been proven to anticipate the onset of breakdown at high...
chapter
In this work we investigate the effects of different interface trap density distributions (Dit) on the electrical and power performances of a Gate-All-Around In0.53Ga0.47As/In0.52Al0.48As Nanowire Superlattice-FETs (GAA NW SL-FET) using Al2O3 and HfO2/La2O3 as gate dielectrics. This analysis shows that a high At content at the high-K/InGaAs interface causes degradation of the subthreshold characteristics...
chapter
We compare band-structure calculations obtained with modeling approaches hierarchically spanning from density functional theory to tight-binding, k·p and non-parabolic effective mass descriptions. We consider III-V quantum-wells with thickness ranging from 3nm to 10nm. Comparison with experiments for unstrained and strained InGaAs quantum-wells is also reported.
article
Solid State Electronics > 2014 > 101 > Complete > 70-78
In this work full-quantum simulations have been employed to devise and optimize both impurity-doped (ID) and electrostatically-doped (ED) superlattice FETs (SL-FETs). A sensitivity investigation to technological and design parameters has been carried out, showing a relatively-low sensitivity to changes of most device parameters. Results at a reduced power supply VDD=0.4V are compared with the ITRS...
article
Solid State Electronics > 2014 > 100 > Complete > 54-60
We study a possible circuit solution to overcome the problem of low voltage gain of short-channel graphene FETs. The circuit consists of a fully differential amplifier with a load made of a cross-coupled transistor pair. Starting from the device characteristics obtained from self-consistent ballistic quantum transport simulations, we explore the circuit parameter space and evaluate the amplifier performance...
chapter
In high-voltage integrated circuits operating at high temperatures, charge transport phenomena can occur in the encapsulation layer as a consequence of the electric field spreading out from the high-voltage bondpads/bondwires. In this work, the most relevant features of epoxy resins commonly used in the high-voltage packaging industry have been modelled and implemented in a commercial TCAD tool. Although...
chapter
Different AC pulsed stress signals have been applied to an n-type LDMOS with shallow-trench isolation (STI). The HCS degradation curves have been measured on wafer by varying frequency and duty-cycle under a high-VDS stress for both low and high Vgs biases. The linear drain current drifts have been also investigated through TCAD predictions under AC stress conditions for the first time. A quantitative...
