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Cu/adhesive hybrid bonding is an attractive approach to three-dimensional (3D) integration because it provides direct CuCu vertical interconnects and high mechanical stability. However, Cu/adhesive hybrid bonding at below 200°C is still challenging because of bonding temperature mismatch between CuCu and polymer adhesives and lacking of effective adhesive-compatible Cu surface activation methods....
Cu/adhesive hybrid bonding is a promising technology to fabricate 3D integrated microsystems with ultra-fine pitch and short vertical interconnects, low electrical resistance, and high reliability. The main remaining issues of this technology include bonding temperature mismatch between Cu-Cu (350–400 °C) and adhesive (typically ≤250 °C), long thermal-compression time (low throughput), and high thermal...
Bump-less Cu/adhesive hybrid bonding is a promising technology for 2.5D/3D integration. The remaining issues of this technology include high Cu–Cu bonding temperature, long thermal-compression time (low throughput), and large thermal stress. In this paper, we investigate a Cu-first hybrid bonding process in hydrogen(H)-containing formic acid (HCOOH) vapor ambient, lowering the bonding temperature...
A large thermal-mechanical stress caused by the mismatch of thermal expansion coefficients (CTEs) between the copper and silicon substrate occurs in the active area of the stacked 3D device using the through-silicon via (TSV). Therefore, the study of TSV-induced stress is of fundamental importance in our understanding of the keep-out zone (KOZ). We investigated the metal-oxide-semiconductor field-effect...
In a lead-free reflow soldering process, it is important to reduce the reflow temperature for low-heat-resistance devices such as optical devices that include organic material. We focused on In-48mass%Sn solder for optical device assembly since the melting point of the solder can be dramatically reduced to 117°C. However, InSn eutectic solder is considered to have poor mechanical properties. Thus,...
For 3D-LSI devices using the through silicon via (TSV) process, there are many reliability issues regarding the large thermal-mechanical stress and deformation volume changes caused by mismatch of the thermal expansion coefficients (CTEs) between the Cu and Si substrate in the device active area. In this paper, we investigated the TSV leakage current in metal-insulator-semiconductors and studies MOSFET...
Three-dimensional chip stacking is a useful integration technology for improving electrical performance. In this study, we manufactured two different-sized stacked chips and examined the stacking process and electrical properties of a Cu pillar joint with a through-silicon via (TSV). To achieve alignment accuracy, a stacking process using reflow with reduction atmosphere was evaluated. As a result,...
Modeling and controlling of warpages and layout-dependent local-deformations are challenges to overcome to realize 3D stacking of dies with through-silicon vias and micro-bumps. Dies larger than about 500 mm2 are now being used for high performance computing, and large cylindrical warpage of the die and local die surface deformations can greatly affect the yield and reliability of the stacked dies...
We have developed Cu-Cu/adhesives hybrid bonding technique by using collective cutting of Cu bumps and adhesives in order to achieve high density 2.5D/3D integration. It is considered that progression of high density interconnection leads to lower height of bonding electrodes, resulting in narrow gap between ICs. Therefore, it is difficult to fill in adhesive to such a narrow gap ICs after bonding...
Investigation of the thermo-mechanical stress by using finite element analysis (FEA) and the destruction verification with thermal cycle (TC) test were carried out. It was found that the back end of line (BEOL) dielectric layer near the through silicon via (TSV) was cracked in case of a RT-400 °C heat cycle. Thermo-mechanical stress concentration at the TSV landing area has been confirmed by the results...
In this paper, a low temperature Cu-Cu direct bonding method is demonstrated even at 175 degree C, which is less than solder melting point, by using fine crystalized bump surface and dedicated surface treatments. Our technique includes introducing fine crystal structure on Cu bump surface by ultra-precision cutting for bump planarization, not using conventional CMP method. This fine crystal structure...
Three-dimensional chip stacking technology is expected to be a powerful method for achieving a short wiring distance between chips, and high-density integration of the functions in the chip, and to achieve the next generation's high-performance large-scale integration (LSI). Each vertically stacked chip is connected by a metal line that penetrates in Si that is called a TSV (Through Silicon Via)....
This paper reports on second-level interconnection development for a large-scale Ball Grid Array (BGA) package. Generally, control of warpage becomes a problem as BGA packages become larger. To solve this problem, the following two measures were executed. The first was adoption of a low-temperature solder, and the second was warpage control using a heat spreader as a fixture. We were able to decrease...
In order to improve the mechanical reliability of IC packages crack generation and its propagation which are caused by such as Chip Package Interaction (CPI) are being investigated by various simulation methods. In this study, Smoothed-particle hydrodynamics (SPH) were first applied to analyze the crack propagation in a solder ball in a Flip Chip Ball Grid Array (FCBGA). SPH simulation is a meshless...
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