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This paper presents a 3-FET stacked K/Ka-band class-AB power amplifier (PA) implemented in the GLOBALFOUNDRIES 45nm SOI process that is particularly optimized for future high-performance energy-efficient 5G mm-Wave transceiver front-ends. With a 2.9V power supply, the PA achieves 13.1dB power gain and a saturated output power (Psat) of 16.2dBm with a maximum power-added efficiency (PAE) of 41.5% at...
In this paper, we first analyze an LNA core, cascode structure cut off frequency and power gain relationship with device parameters. Then we discuss the LNA design differences between FET LNA and SiGe LNA during design optimization. SOI floating body FETs have advantages in higher Ft in the optimized current biased region and can offer more design flexibility, while SiGe NPNs need much less trade...
Breakdown voltage and RF characteristics relevant for RF power amplifiers (PA) are presented in this paper. Typically, DC collector-to-emitter breakdown voltage with base open (BVCEO) or DC collector-to-base breakdown with emitter open (BVCBO) has been presented as the metric for voltage limit of PA devices. In practical PA circuits, the RF envelope voltage can swing well beyond BVCEO without causing...
This chapter focuses on some of the radiofrequency (RF) and millimetre-wave (MMW) applications that a through-silicon via (TSV) technology can enable. We will first discuss a grounded TSV application for a RF wireless communication power amplifier that is in mass production. A grounded TSV is essentially a metal connection that takes the active device interconnect to a package ground without needing...
In this paper, we present 2.4/5.5 GHz LNAs with SPDT Switch for WiFi Front-End Modulate Integrated Circuit (FEM IC) based on high resistivity substrate 0.35um SiGe BiCMOS process. For the 2.4GHz LNA, the bias circuit's effect on the nonlinearity is analyzed and measured, and then a new bias circuit is proposed. With 2.7V supply, it consumes 4.2mA current. The measured Gain is about 14.6dB with input...
Over the past few years, CMOS Silicon-oninsulator (SOI) has emerged as the dominant technology for RF switches in RF front end modules for cell phones and WiFi. RF SOI technologies were created from silicon processes originally used for high speed logic applications, but the technology was modified to meet the performance needs of RF switches. The RF SOI technologies have been improved to follow the...
IBM first qualified a 0.35μm generation 1000 Ω-cm high resistivity substrate (HiRES) SiGe BiCMOS technology in 2011. This technology was optimized for WiFi and cellular NPN power amplifier (PA), NPN low noise amplifier (LNA), and isolated CMOS NFET switch rf front-end-IC (FEIC) integration. It includes an optional through silicon via used as a low inductance ground path for NPN emitters. Data for...
This paper discusses concurrent design and analysis of the first 8.5 kV electrostatic discharge (ESD) protected single-pole ten-throw (SP10T) transmit/receive (T/R) switch for quad-band (0.85/0.9/1.8/1.9 GHz) GSM and multiple-band WCDMA smartphones. Implemented in a 0.18 m SOI CMOS, this SP10T employs a series-shunt topology for the time-division duplex (TDD) transmitting (Tx) and receiving (Rx),...
Silicon technologies have continued to usurp other exotic technologies, such as GaAs and Silicon-on-Sapphire (SOS), from the RF wireless communication system to provide a more cost-effective integration path. The integration of RF front-end (RFFE) electronics is a good example of this trend. RFFE components such as, transmit-receive switch, antenna tuners, low-noise amplifiers, and power amplifiers,...
Design of single-pole multiple-throw (SPMT) Tx/Rx switch for RF FEM for multi-mode multi-frequency smartphones is challenging. SPMTs in SOI CMOS show comparable specs to those in GaAs due to unique SOI properties [1-3]. Hand-held devices require high ESD protection with more parasitic capacitance (CESD) that can severely degrade RF IC specs [4-6]. We recently designed the first highly-linearity SP10T...
This paper reports the first 8kV+ ESD-protected SP10T transmit/receive (T/R) antenna switch for quad-band (0.85/0.9/1.8/1.9-GHz) GSM and multiple W-CDMA smartphones fabricated in an 180-nm SOI CMOS. A novel physics-based switch-ESD co-design methodology is applied to ensure full-chip optimization for a SP10T test chip and its ESD protection circuit simultaneously.
We present for the first time a novel high resistivity bulk SiGe BiCMOS technology that has been optimized for a WiFi RF front-end-IC (FEIC) integration. A nominally 1000 Ohm-cm p-type silicon substrate is utilized to integrate several SiGe HBTs for power amplifiers (PAs), a SiGe HBT low-noise amplifier (LNA), and isolated nFET RF switch device. Process elements include trench isolation for low-loss...
In this study, we define and investigate the maximum power handling capability (Pmax) in an SOI RF shunt branch switch. One of the critical factor in the Pmax is the non-uniform voltage division across an OFF shunt branch. In this study we provide a simple analytical method to determine the stack voltage imbalance. The Pmax is characterized as a function of various parameters, such as, switch stack...
This paper presents a comparative analysis of four different multiplier architectures. The four multipliers include the array multiplier, a bypass multiplier with tree structure, a multiplier with 2-d bypass, and a bypass multiplier using improved column bypassing schemes. The multipliers a reimplemented in 90nm CMOS technology. The architectures are compared in terms of critical path delay, power...
The advancement of modern computing machines today is seen in embedded systems by making the system do more functions faster and in real time. One technique is to use multiple processors executing in parallel. Also, because embedded systems have limited memory size, adding more functions in the system will limit the data that can be stored in the memory. This project is an implementation of a compiler...
On behalf of the Executive Committee, we would like to welcome you to the 2010 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM). The BCTM 2010 will be held 4th∓6th October, 2010 at the Radisson Hotel & Suites Austin-Town Lake. It includes a one day short course and two days of the conference.
On-chip Wilkinson power dividers are used in MMW circuit designs such as phased array antenna systems. This paper presents a novel on-chip MMW Through-Silicon-Via (TSV) Wilkinson power divider. HFSS simulations of the TSV Wilkinson power divider in a 130 nm BiCMOS technology revealed insertion loss per λ/4 “arm” of 0.9 dB at 60 GHz with both return loss and isolation better than 18 dB at 60 GHz and...
A new negative differential resistance (NDR) effect is reported for the first time in cryogenically-operated SiGe HBTs. A physical explanation based on heterojunction barrier effect (HBE) is presented, and confirmed using calibrated 2-D TCAD simulations. The ac consequences of this NDR effect and the impact of technology scaling on the phenomenon are also addressed
Factors contributing to the observed bias-dependent features in common-base (CB) DC instability characteristics are examined for advanced SiGe HBTs. Parameters relevant to CB instabilities are identified and extracted from data to yield improved physical insight, a straightforward estimation methodology, and simple comparison between samples
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