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IBM first qualified a 0.35μm generation 1000 Ω-cm high resistivity substrate (HiRES) SiGe BiCMOS technology in 2011. This technology was optimized for WiFi and cellular NPN power amplifier (PA), NPN low noise amplifier (LNA), and isolated CMOS NFET switch rf front-end-IC (FEIC) integration. It includes an optional through silicon via used as a low inductance ground path for NPN emitters. Data for...
This paper discusses concurrent design and analysis of the first 8.5 kV electrostatic discharge (ESD) protected single-pole ten-throw (SP10T) transmit/receive (T/R) switch for quad-band (0.85/0.9/1.8/1.9 GHz) GSM and multiple-band WCDMA smartphones. Implemented in a 0.18 m SOI CMOS, this SP10T employs a series-shunt topology for the time-division duplex (TDD) transmitting (Tx) and receiving (Rx),...
This paper reports the first 8kV+ ESD-protected SP10T transmit/receive (T/R) antenna switch for quad-band (0.85/0.9/1.8/1.9-GHz) GSM and multiple W-CDMA smartphones fabricated in an 180-nm SOI CMOS. A novel physics-based switch-ESD co-design methodology is applied to ensure full-chip optimization for a SP10T test chip and its ESD protection circuit simultaneously.
We present for the first time a novel high resistivity bulk SiGe BiCMOS technology that has been optimized for a WiFi RF front-end-IC (FEIC) integration. A nominally 1000 Ohm-cm p-type silicon substrate is utilized to integrate several SiGe HBTs for power amplifiers (PAs), a SiGe HBT low-noise amplifier (LNA), and isolated nFET RF switch device. Process elements include trench isolation for low-loss...
In this study, we define and investigate the maximum power handling capability (Pmax) in an SOI RF shunt branch switch. One of the critical factor in the Pmax is the non-uniform voltage division across an OFF shunt branch. In this study we provide a simple analytical method to determine the stack voltage imbalance. The Pmax is characterized as a function of various parameters, such as, switch stack...
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