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In this paper, different Hf-based oxides (HfO2, HfSiO under several annealing conditions, HfSiON, HfAlO with various compositions) are simultaneously considered as storage layers of charge-trap memories. Based on material characterization analyses, electrical data of memory cells, physical modeling of charge-trap devices, we show that a strict relationship exists between the crystal structure of the...
In this article, we report improved results of 4-bit double SONOS memories (DSMs) with 4-storage nodes through the optimization of ONO layer thicknesses for front and back sides. They show more balanced characteristics between the front and back channels, higher VTH shifts above 2.4V, larger read margins above 1.6V, better endurance, and longer retention time than our previous results. In addition,...
Electroporation is a widely used technique which allows introducing into cultured cells molecules which won't enter in naturally because of the high selectivity of the cell membrane (this is called transfection). We are presenting in this paper a biochip comprising an array of microelectrodes which can be used to electroporate single cells instead than the large number of cells customarily treated...
A high density GMR sensor array was integrated with a standard CMOS chip for DNA hybridization detection. Absorption of magnetic nanoparticles by the hybridized DNA alters the sensor resistance, and generated electrical signals are directly measured with the on-die circuitry. The proposed biochip can be applied to other bio-reaction detection, e.g. protein assay, through different surface modifications
The authors present for the first time the full integration scheme and 512Mb product data for a trench DRAM technology targeting the 58nm node. The key technology enablers such as an extended U-shape cell device (EUD), high performance support devices, trench capacitor with metal-insulator-silicon (MIS)/high-k dielectric and metal-in-collar (MIC), and low-k inter-level dielectric (ILD) are demonstrated
An aggressively scaled, self-aligned, independently controlled double-gate floating body cell (IDG FBC) is reported. This structure eases the scaling constraints of other FBC memory devices proposed to date. Enhanced memory performance has been demonstrated owing to the independent back gate with thin oxide and thin Si fin. Memory devices with 85-nm Lg and 30-nm fin widths (Z) have been shown to exhibit...
A 3D packaging technology has been developed for 4 Gbit DRAM. Highly-doped poly-Si through-silicon vias (TSVs) are used for vertical traces inside silicon and interconnection between DRAM chips to realize a DRAM compatible process. Through optimization of the process conditions and layout design, fast poly-Si filling has been obtained. The entire packaging was carried out at the wafer level by using...
AlGaN/GaN HFET devices demonstrate remarkable performance. For commercial acceptance of this technology, long-term device stability must meet stringent industry standards. We review the current status of GaN reliability and contrast it with the requirement for commercial viability. Results analyzing degradation pertaining to buffer leakage and gate diode forward failure is presented
Since nitrided oxides improve gate leakage at the expense of NBTI, one must optimize nitrogen concentration in oxinitride samples for reliable performance and reduced power dissipation. Here, we analyze wide range of NBTI stress data to develop a predictive model for gate leakage and first self-consistent model for field acceleration within R-D framework. This model anticipates a novel design diagram...
We present an advanced CMOS integration scheme based on embedded SiGe (eSiGe) with a novel graded germanium process. The retention of channel strain enabled a pFET performance gain of 15% over a non-graded eSiGe control. When combined with a compressive stress liner (CSL), the pFET drive current reached 770muA/mum at Ioff = 100nA/mum with VDD = 1V. Competitive nFET performance was maintained. Parasitics...
Ultra low power circuit operation is demonstrated with dopant segregated Schottky (DSS) source/drain transistors for the first time. DSS greatly improves propagation delay in multiple fan-in NAND gates at constant standby current. The delay is enhanced to 21% at 0.8V for 3-input NAND gates. Energy delay product (EDP) is improved by more than 50% with DSS at 0.8V
A study was performed to investigate the effect of multiple stressors on CMOS devices on (110) and (100) substrates with different channel directions. For the first time, 87% ION-IOFF improvement is achieved by utilizing SiGe-S/D and compressive contact etch stop layer (c-CESL) for PMOS devices on (110) substrate with lang111'rang channel direction. The improvement is similar to that on conventional...
Two integration schemes for hybrid crystal orientation technology using direct silicon bonded (DSB) substrates and solid phase epitaxy (SPE) processes have been implemented. The shallow-trench-isolation (STI) before SPE approach suffers from trench-edge defects formed at STI edges, which causes high leakage current. The SPE-before-STI approach allows removal of edge defects of SPE by STI. SRAM in...
The short length effect on the electromigration (EM) lifetime is a valuable resource to increase current limits in advanced circuits. We model the effect with variable (current density j sensitive) current exponent n for short leads and calculate how much lifetime margin should be observed for a certain EM rule relaxation. The shorter leads have larger (variable) n so that the EM lifetime decreases...
The performance of novel AlInN/GaN HEMTs for high power / high temperature applications is discussed. With 0.25 mum gate length the highest maximum output current density of more than 2 A/mm at room temperature and more than 3 A/mm at 77 K have been obtained even with sapphire substrates. Cut-off frequencies were fT = 50 GHz and fMAX = 60 GHz for 0.15 mum gate length without T-gate. Pulsed measurements...
The authors demonstrate a novel CMP-less FUSI integration scheme which uses a spin-on sacrificial material for planarization showing 45nm gate length Ni-rich FUSI pMOS and NiSi FUSI nMOS transistors on HfSiON. This new scheme does not require CMP but remains compatible with phase-controlled dual-WF CMOS with independent silicidation of the S/D and the gate. This approach uses very selective dry etch...
Multiple gate field effect transistors (MuGFET) with a fin pitch down to 50nm obtained with 193nm optical lithography and proposed fin quadrupling patterning method are demonstrated. The fins patterned with this technique feature improved CD control and line width roughness. High fin density in combination with Si-SEG that allows merging individual fins outside the spacer region lead to reduction...
This paper compares the performance and inter-die variability of doped and undoped channel multiple-gate FETs (MUGFETs) with respect to planar SOI devices. We show that doped-channel FinFETs have equivalent variability to narrow-width planar devices. As such, transitions to FinFETs for narrow-width devices will likely incur minimal variability impact. To match the low variability of wide-width planar...
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